Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Mos6502

T6502

ctrl

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      T6502_ctrl

      fs-common

        ../verilog/top.rtl

        verilogSourcefragment

      fs-sim

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/common/T6502_ctrl

        verilogSourcemodule

      fs-syn

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/common/T6502_ctrl

        verilogSourcemodule

                                Hierarchical

              Hierarchical

                 Hierarchical

              logic_ctrl

                                   ipxact:library="Mos6502"

                                   ipxact:name="T6502"

                                   ipxact:version="logic_ctrl"/>

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

     common:*common:*

     Verilog

     fs-common

     sim:*Simulation:*

     Verilog

     fs-sim

     syn:*Synthesis:*

     Verilog

     fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

clk

wire

in

mem_wdata

wire

in150

mem_rdata

wire

out150

pg0_add

wire

in71