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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Mos6502
T6502
def
 

 
 slave_clk
  
  
      
        
    
      
        clk
        clk
      
    
      
      
  
 
 
 
 
 slave_reset
  

      
        
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 jtag
 

      
  
    
 
      
        shiftcapture_dr_clk
        jtag_shiftcapture_dr_clk
      
 
 
      
        test_logic_reset
        jtag_test_logic_reset
      
 
      
        capture_dr
        jtag_capture_dr
      
 
      
        shift_dr
        jtag_shift_dr
      
 
      
        update_dr_clk
        jtag_update_dr_clk
      
 
 
      
        tdi
        jtag_tdi
      
 
      
        tdo
        jtag_tdo
      
 
      
        select
        jtag_select
      
 
    
 
      
      
  
 
 
 
 
 

 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      T6502_def
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 

 

    BOOT_ROM_WIDTH16
    ROM_WRITETHRU0
    ADDR11

 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
   
 
 
              
              Hierarchical
                Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
     
     common:*common:*
     Verilog
     
     
 
 
 
 
 
 
     
     sim:*Simulation:*
      Verilog
     
     fs-sim
     
 
     
     syn:*Synthesis:*
      Verilog
     
     fs-sim
     
 
 
     
     syn2:*Synthesis:*
      Verilog
     
     fs-syn
     
 
 
 
 
              
              doc:*Documentation:*
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
 
              Verilog
              
 
 
 
 
   
 
 
 

 
 

ext_addr
wire
out231

 

ext_wdata
wire
out150

 

ext_rdata
wire
in150

 
 

ext_ub
wire
out

 
ext_wait
wire
in

 
ext_lb
wire
out

 
ext_rd
wire
out

 
ext_stb
wire
out

 
ext_wr
wire
out

 
ext_cs
wire
out10

 
 
alu_status
wire
out70

 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
 
gpio_0_out
wire
out70

 
gpio_0_oe
wire
out70

 
 
gpio_0_in
wire
in70

 
gpio_1_out
wire
out70

 
gpio_1_oe
wire
out70

 
 
gpio_1_in
wire
in70

 
ext_irq_in
wire
in30

 
 
 
 
jsp_data_out
wire
out70

 
 
 
wb_jsp_dat_i
wire
in70

 
 
biu_wr_strobe
wire
out

 
 
wb_jsp_stb_i
wire
in

 
 
 
 
 

 

 
 
 
 
 

 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/T6502_def
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/syn.v
        verilogSourceinclude
      
 
 
 
   
 
 

 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton	`slave_clk`
45
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58	131	jt_eaton
59	135	jt_eaton
60	131	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	131	jt_eaton
78
79	135	jt_eaton	`jtag`
80
81
82
83
84
85	131	jt_eaton
86	135	jt_eaton
87			`shiftcapture_dr_clk`
88			`jtag_shiftcapture_dr_clk`
89
90	131	jt_eaton
91
92	135	jt_eaton
93			`test_logic_reset`
94			`jtag_test_logic_reset`
95
96	131	jt_eaton
97	135	jt_eaton
98			`capture_dr`
99			`jtag_capture_dr`
100
101	131	jt_eaton
102	135	jt_eaton
103			`shift_dr`
104			`jtag_shift_dr`
105
106	131	jt_eaton
107	135	jt_eaton
108			`update_dr_clk`
109			`jtag_update_dr_clk`
110
111	131	jt_eaton
112
113	135	jt_eaton
114			`tdi`
115			`jtag_tdi`
116
117	131	jt_eaton
118	135	jt_eaton
119			`tdo`
120			`jtag_tdo`
121
122	131	jt_eaton
123	135	jt_eaton
124			`select`
125			`jtag_select`
126
127	131	jt_eaton
128	135	jt_eaton
129	131	jt_eaton
130	135	jt_eaton
131
132
133	131	jt_eaton
134	135	jt_eaton
135	131	jt_eaton
136
137
138	135	jt_eaton
139	131	jt_eaton
140
141	135	jt_eaton
142	131	jt_eaton
143
144	135	jt_eaton
145			`gen_verilog`
146			`104.0`
147			`none`
148			`:common:`
149			`tools/verilog/gen_verilog`
150
151
152			`destination`
153			`T6502_def`
154
155
156
157	131	jt_eaton
158
159
160
161
162
163
164
165
166	135	jt_eaton
167	131	jt_eaton
168
169
170
171
172	135	jt_eaton
173	131	jt_eaton
174	135	jt_eaton
175	131	jt_eaton
176	135	jt_eaton
177			`BOOT_ROM_WIDTH16`
178			`ROM_WRITETHRU0`
179			`ADDR11`
180
181	131	jt_eaton
182
183
184	135	jt_eaton
185
186			`Hierarchical`
187
188
189
190	131	jt_eaton
191
192
193
194	135	jt_eaton
195
196	131	jt_eaton
197
198	135	jt_eaton
199			`Hierarchical`
200			`Hierarchical`
201	131	jt_eaton
202	135	jt_eaton
203	131	jt_eaton
204
205	135	jt_eaton
206			`verilog`
207
208
209			`ipxact:library="Testbench"`
210			`ipxact:name="toolflow"`
211			`ipxact:version="verilog"/>`
212
213
214	131	jt_eaton
215
216
217
218
219
220	135	jt_eaton
221			`common:common:`
222			`Verilog`
223
224
225	131	jt_eaton
226
227
228
229
230
231	135	jt_eaton
232			`sim:Simulation:`
233			`Verilog`
234
235			`fs-sim`
236
237	131	jt_eaton
238	135	jt_eaton
239			`syn:Synthesis:`
240			`Verilog`
241
242			`fs-sim`
243
244	131	jt_eaton
245
246	135	jt_eaton
247			`syn2:Synthesis:`
248			`Verilog`
249
250			`fs-syn`
251
252	133	jt_eaton
253	131	jt_eaton
254
255
256	135	jt_eaton
257			`doc:Documentation:`
258
259
260			`ipxact:library="Testbench"`
261			`ipxact:name="toolflow"`
262			`ipxact:version="documentation"/>`
263
264	131	jt_eaton
265	135	jt_eaton	`Verilog`
266
267	131	jt_eaton
268
269
270
271	135	jt_eaton
272	131	jt_eaton
273
274
275	135	jt_eaton
276	131	jt_eaton
277
278	135	jt_eaton
279			`ext_addr`
280			`wire`
281			`out231`
282
283	131	jt_eaton
284	135	jt_eaton
285			`ext_wdata`
286			`wire`
287			`out150`
288
289	131	jt_eaton
290	135	jt_eaton
291			`ext_rdata`
292			`wire`
293			`in150`
294
295	131	jt_eaton
296
297	135	jt_eaton
298			`ext_ub`
299			`wire`
300			`out`
301
302	131	jt_eaton
303	135	jt_eaton	`ext_wait`
304			`wire`
305			`in`
306
307	131	jt_eaton
308	135	jt_eaton	`ext_lb`
309			`wire`
310			`out`
311
312	131	jt_eaton
313	135	jt_eaton	`ext_rd`
314			`wire`
315			`out`
316
317	131	jt_eaton
318	135	jt_eaton	`ext_stb`
319			`wire`
320			`out`
321
322	131	jt_eaton
323	135	jt_eaton	`ext_wr`
324			`wire`
325			`out`
326
327	131	jt_eaton
328	135	jt_eaton	`ext_cs`
329			`wire`
330			`out10`
331
332	131	jt_eaton
333
334	135	jt_eaton	`alu_status`
335			`wire`
336			`out70`
337
338	131	jt_eaton
339	135	jt_eaton	`cts_pad_in`
340			`wire`
341			`in`
342
343	131	jt_eaton
344	135	jt_eaton	`rts_pad_out`
345			`wire`
346			`out`
347
348	131	jt_eaton
349
350	135	jt_eaton	`gpio_0_out`
351			`wire`
352			`out70`
353
354	131	jt_eaton
355	135	jt_eaton	`gpio_0_oe`
356			`wire`
357			`out70`
358
359	131	jt_eaton
360
361	135	jt_eaton	`gpio_0_in`
362			`wire`
363			`in70`
364
365	131	jt_eaton
366	135	jt_eaton	`gpio_1_out`
367			`wire`
368			`out70`
369
370	131	jt_eaton
371	135	jt_eaton	`gpio_1_oe`
372			`wire`
373			`out70`
374
375	131	jt_eaton
376
377	135	jt_eaton	`gpio_1_in`
378			`wire`
379			`in70`
380
381	131	jt_eaton
382	135	jt_eaton	`ext_irq_in`
383			`wire`
384			`in30`
385
386	131	jt_eaton
387
388
389
390	135	jt_eaton	`jsp_data_out`
391			`wire`
392			`out70`
393
394	131	jt_eaton
395
396
397	135	jt_eaton	`wb_jsp_dat_i`
398			`wire`
399			`in70`
400
401	131	jt_eaton
402
403	135	jt_eaton	`biu_wr_strobe`
404			`wire`
405			`out`
406
407	131	jt_eaton
408
409	135	jt_eaton	`wb_jsp_stb_i`
410			`wire`
411			`in`
412
413	131	jt_eaton
414
415
416
417
418	135	jt_eaton
419	131	jt_eaton
420	135	jt_eaton
421
422	131	jt_eaton
423
424
425
426	135	jt_eaton
427	131	jt_eaton
428
429	135	jt_eaton
430			`fs-sim`
431	131	jt_eaton
432	135	jt_eaton
433
434			`../verilog/copyright.v`
435			`verilogSourceinclude`
436
437	131	jt_eaton
438	135	jt_eaton
439
440			`../verilog/common/T6502_def`
441			`verilogSourcemodule`
442
443	131	jt_eaton
444
445
446	135	jt_eaton
447	131	jt_eaton
448	135	jt_eaton
449			`fs-syn`
450	131	jt_eaton
451	135	jt_eaton
452
453			`../verilog/syn.v`
454			`verilogSourceinclude`
455
456	131	jt_eaton
457
458
459	135	jt_eaton
460	131	jt_eaton
461
462	135	jt_eaton
463	131	jt_eaton
464
465
466
467
468
469
470
471
472	135	jt_eaton
473
474
475
476
477	131	jt_eaton
478
479