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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_logic_ctrl.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Mos6502
T6502
logic_ctrl
 
 

 

 
 

mem_cs
wire
in

 
 
 
 
mem_wr
wire
in

 
 
 
mem_rd
wire
in

 
 
pg0_wr
wire
in

 
 
 
pg0_rd
wire
in

 
 
 
 
 
 
 

pg0_add
wire
in00

 
 
 
 

mem_addr
wire
in00

 
 
 
 
 

timer_irq
wire
in10

 
 
 
rx_irq
wire
in

 
 
tx_irq
wire
in

 
 
ps2_data_avail
wire
in

 
 
 
ext_irq_in
wire
in20

 
 
 

cpu_pg0_data
wire
out70

 
 
 
 

io_module_pic_irq_in
wire
out70

 
 
 

io_module_vic_irq_in
wire
out70

 
 

 

 
 
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`logic_ctrl`
41
42
43
44
45
46
47
48
49			`mem_cs`
50			`wire`
51			`in`
52
53
54
55
56
57			`mem_wr`
58			`wire`
59			`in`
60
61
62
63
64			`mem_rd`
65			`wire`
66			`in`
67
68
69
70			`pg0_wr`
71			`wire`
72			`in`
73
74
75
76
77			`pg0_rd`
78			`wire`
79			`in`
80
81
82
83
84
85
86
87
88
89			`pg0_add`
90			`wire`
91			`in00`
92
93
94
95
96
97
98			`mem_addr`
99			`wire`
100			`in00`
101
102
103
104
105
106
107
108			`timer_irq`
109			`wire`
110			`in10`
111
112
113
114
115			`rx_irq`
116			`wire`
117			`in`
118
119
120
121			`tx_irq`
122			`wire`
123			`in`
124
125
126
127			`ps2_data_avail`
128			`wire`
129			`in`
130
131
132
133
134			`ext_irq_in`
135			`wire`
136			`in20`
137
138
139
140
141
142			`cpu_pg0_data`
143			`wire`
144			`out70`
145
146
147
148
149
150
151			`io_module_pic_irq_in`
152			`wire`
153			`out70`
154
155
156
157
158
159			`io_module_vic_irq_in`
160			`wire`
161			`out70`
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_logic_ctrl.xml] - Blame information for rev 135