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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
Mos6502
core
 
 
2
_
_
_
VARIANT
 

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 
 

 
         
            default
            def
            
            VEC_TABLE8'hff
            BOOT_VEC8'hfc
           
          
      
 
 
 

 
 
core/sim
 

 
 
 
 

 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`Mos6502`
12			`core`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21	135	jt_eaton
22
23			`TestBenches`
24			`sim`
25			`testbenches`
26			`testbench`
27			`version`
28
29
30			`Fpgas`
31			`syn`
32			`ise`
33			`chip`
34			`variant`
35
36
37	131	jt_eaton
38	135	jt_eaton
39
40	131	jt_eaton
41
42			`/doc`
43
44
45
46
47	134	jt_eaton
48	131	jt_eaton
49	134	jt_eaton
50			`default`
51			`def`
52
53			`VEC_TABLE8'hff`
54			`BOOT_VEC8'hfc`
55
56
57
58	131	jt_eaton
59	134	jt_eaton
60
61	131	jt_eaton
62
63
64			`core/sim`
65
66
67
68
69
70
71
72
73

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [componentCfg.xml] - Blame information for rev 135