Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Mos6502

core

def

 slave_clk

        clk

        clk

 slave_reset

        reset

        reset

 cpu

        addr

        addr

        150

        rdata

        rdata

        150

        wdata

        wdata

        70

        rd

        rd

        wr

        wr

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      core_def

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      core_def

      fs-sim

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/sim/core_def

        verilogSourcemodule

        ../verilog/defines

        verilogSourceinclude

        alu

        ../verilog/alu

        verilogSourcemodule

        alu_logic

        ../verilog/alu_logic

        verilogSourcemodule

        control

        ../verilog/control

        verilogSourcemodule

        inst_decode

        ../verilog/inst_decode

        verilogSourcemodule

        sequencer

        ../verilog/sequencer

        verilogSourcemodule

        state_fsm

        ../verilog/state_fsm

        verilogSourcemodule

        ../verilog/top.sim

        verilogSourcefragment

        ../verilog/top.body

        verilogSourcefragment

      fs-syn

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/syn/core_def

        verilogSourcemodule

        ../verilog/defines

        verilogSourceinclude

        alu

        ../verilog/alu

        verilogSourcemodule

        alu_logic

        ../verilog/alu_logic

        verilogSourcemodule

        control

        ../verilog/control

        verilogSourcemodule

        inst_decode

        ../verilog/inst_decode

        verilogSourcemodule

        sequencer

        ../verilog/sequencer

        verilogSourcemodule

        state_fsm

        ../verilog/state_fsm

        verilogSourcemodule

        ../verilog/top.body

        verilogSourcefragment

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

       sim:*Simulation:*

       Verilog

       fs-sim

       syn:*Synthesis:*

       Verilog

       fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

clk

wire

in

reset

wire

in

enable

wire

in

addr

wire

out

wdata

wire

out

rdata

wire

in

rd

wire

out

wr

wire

out

nmi

wire

in

vec_int

wire

in

70

prog_data

wire

in

150

pg0_data

wire

in

70

alu_status

wire

out

70

prog_counter

wire

out

150

pg0_add

wire

out

70

pg0_rd

wire

out

pg0_wr

wire

out

stk_push

wire

out

stk_push_data

wire

out

150

stk_pull

wire

out

stk_pull_data

wire

in

150