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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Mos6502
cpu
def
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
      
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
 
 
 
 cpu
  
  
      
  
    
      
        addr
        addr
        150
        
      
      
        rdata
        rdata
        150
        
      
      
        wdata
        wdata
        70
        
      
      
        rd
        rd
        
      
      
        wr
        wr
        
      
    
      
      
           
 
 
 

 
 

  
    cpu
    0x10000
    8
  

 
 
 
 
 

 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
  
    
      destination
      cpu_def
    
  

 
 
 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/sim/cpu_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/sim/cpu_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
  
 
        
                        
                                Hierarchical
                                
                        
                
 
 
 
       
 
 
              
              Hierarchical
              Hierarchical
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
       
       sim:*Simulation:*
       Verilog
       
       fs-sim
       
 
 
       
       syn:*Synthesis:*
       Verilog
       
       fs-syn
       
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 PROG_ROM_WIDTH16
 STACK_RAM_SIZE8
 STACK_RAM_WORDS256
 STACK_RAM_WIDTH16
 

 
 
 

 
 
 
clk
wire
in

 
reset
wire
in

 
enable
wire
in

 
 
addr
wire
out

 
 
wdata
wire
out

 
rdata
wire
in

 
 
rd
wire
out

 
 
wr
wire
out

 
nmi
wire
in

 
vec_int
wire
in
70

 
 
 
 
pg0_data
wire
in
70

 
alu_status
wire
out
70

 
 
pg0_add
wire
out
70

 
pg0_rd
wire
out

 
pg0_wr
wire
out

 
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Mos6502`
39			`cpu`
40			`def`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton	`slave_clk`
45
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58
59	131	jt_eaton
60
61	135	jt_eaton	`slave_reset`
62
63
64
65
66
67
68			`reset`
69			`reset`
70
71
72
73
74
75	131	jt_eaton
76	135	jt_eaton
77	131	jt_eaton
78
79
80
81	135	jt_eaton
82			`cpu`
83
84
85
86
87
88
89			`addr`
90			`addr`
91			`150`
92
93
94
95			`rdata`
96			`rdata`
97			`150`
98
99
100
101			`wdata`
102			`wdata`
103			`70`
104
105
106
107			`rd`
108			`rd`
109
110
111
112			`wr`
113			`wr`
114
115
116
117
118
119
120	131	jt_eaton
121	135	jt_eaton
122	131	jt_eaton
123	135	jt_eaton
124	131	jt_eaton
125
126	135	jt_eaton
127
128			`cpu`
129			`0x10000`
130			`8`
131
132
133	131	jt_eaton
134
135
136
137
138	135	jt_eaton
139	131	jt_eaton
140	133	jt_eaton
141
142
143
144
145	135	jt_eaton
146			`gen_verilog_sim`
147			`104.0`
148			`none`
149			`:Simulation:`
150			`tools/verilog/gen_verilog`
151
152
153			`destination`
154			`cpu_def`
155
156
157
158	131	jt_eaton
159
160
161
162
163
164	135	jt_eaton
165	131	jt_eaton
166
167
168
169
170	135	jt_eaton
171	131	jt_eaton
172
173	135	jt_eaton
174			`fs-sim`
175	131	jt_eaton
176	135	jt_eaton
177
178			`../verilog/sim/cpu_def`
179			`verilogSourcemodule`
180
181	131	jt_eaton
182
183	135	jt_eaton
184
185			`../verilog/`
186			`verilogSourcelibraryDir`
187
188	131	jt_eaton
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195	135	jt_eaton
196			`fs-syn`
197	131	jt_eaton
198	135	jt_eaton
199
200			`../verilog/sim/cpu_def`
201			`verilogSourcemodule`
202
203	131	jt_eaton
204
205	135	jt_eaton
206
207			`../verilog/`
208			`verilogSourcelibraryDir`
209
210	131	jt_eaton
211
212
213	135	jt_eaton
214	131	jt_eaton
215
216
217
218
219
220	135	jt_eaton
221	131	jt_eaton
222
223
224
225	135	jt_eaton
226	131	jt_eaton
227	135	jt_eaton
228
229			`Hierarchical`
230
231
232
233	131	jt_eaton
234
235	135	jt_eaton
236
237	131	jt_eaton
238
239	135	jt_eaton
240			`Hierarchical`
241			`Hierarchical`
242
243	131	jt_eaton
244	135	jt_eaton
245			`verilog`
246
247
248			`ipxact:library="Testbench"`
249			`ipxact:name="toolflow"`
250			`ipxact:version="verilog"/>`
251
252
253	131	jt_eaton
254
255
256
257
258
259	135	jt_eaton
260			`sim:Simulation:`
261			`Verilog`
262
263			`fs-sim`
264
265	131	jt_eaton
266
267	135	jt_eaton
268			`syn:Synthesis:`
269			`Verilog`
270
271			`fs-syn`
272
273	131	jt_eaton
274
275
276	135	jt_eaton
277			`doc`
278
279
280			`ipxact:library="Testbench"`
281			`ipxact:name="toolflow"`
282			`ipxact:version="documentation"/>`
283
284			`:Documentation:`
285			`Verilog`
286
287	131	jt_eaton
288
289	135	jt_eaton
290	133	jt_eaton
291	131	jt_eaton
292
293	135	jt_eaton
294			`PROG_ROM_WIDTH16`
295			`STACK_RAM_SIZE8`
296			`STACK_RAM_WORDS256`
297			`STACK_RAM_WIDTH16`
298	131	jt_eaton
299	135	jt_eaton
300	131	jt_eaton
301
302
303	135	jt_eaton
304	131	jt_eaton
305
306
307	135	jt_eaton	`clk`
308			`wire`
309			`in`
310
311	131	jt_eaton
312	135	jt_eaton	`reset`
313			`wire`
314			`in`
315
316	131	jt_eaton
317	135	jt_eaton	`enable`
318			`wire`
319			`in`
320
321	131	jt_eaton
322
323	135	jt_eaton	`addr`
324			`wire`
325			`out`
326
327	131	jt_eaton
328
329	135	jt_eaton	`wdata`
330			`wire`
331			`out`
332
333	131	jt_eaton
334	135	jt_eaton	`rdata`
335			`wire`
336			`in`
337
338	131	jt_eaton
339
340	135	jt_eaton	`rd`
341			`wire`
342			`out`
343
344	131	jt_eaton
345
346	135	jt_eaton	`wr`
347			`wire`
348			`out`
349
350	131	jt_eaton
351	135	jt_eaton	`nmi`
352			`wire`
353			`in`
354
355	131	jt_eaton
356	135	jt_eaton	`vec_int`
357			`wire`
358			`in`
359			`70`
360
361	131	jt_eaton
362
363
364
365	135	jt_eaton	`pg0_data`
366			`wire`
367			`in`
368			`70`
369
370	131	jt_eaton
371	135	jt_eaton	`alu_status`
372			`wire`
373			`out`
374			`70`
375
376	131	jt_eaton
377
378	135	jt_eaton	`pg0_add`
379			`wire`
380			`out`
381			`70`
382
383
384			`pg0_rd`
385			`wire`
386			`out`
387
388
389			`pg0_wr`
390			`wire`
391			`out`
392
393
394
395
396
397
398
399
400
401
402
403
404
405