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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
adv_debug_sys
adv_dbg_if
 
 
 
2
_
_
_
VARIANT

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/Hardware/adv_dbg_if/doc
 

 
 

 
 
adv_dbg_if/sim
 
 
 

 
 
 

adv_dbg_if_cpu0_tb
cpu0_tb

    PERIOD40
    TIMEOUT100000


  
  adv_dbg_if_cpu0TB.test.dut
  


  icarus
  coverage


 
 
 

adv_dbg_if_cpu1_tb
cpu1_tb

    PERIOD40
    TIMEOUT100000


  
  adv_dbg_if_cpu1TB.test.dut
  


  icarus
  coverage


 
 
 
 
 
 

adv_dbg_if_jsp_tb
jsp_tb

    PERIOD40
    TIMEOUT100000


  
  adv_dbg_if_jspTB.test.dut
  


  icarus
  coverage


 
 

adv_dbg_if_jfifo_tb
jfifo_tb

    PERIOD40
    TIMEOUT100000


  
  adv_dbg_if_jfifoTB.test.dut
  


  icarus
  coverage


 
 
 

adv_dbg_if_jfifo_sync_tb
jfifo_sync_tb

    PERIOD40
    TIMEOUT100000


  
  adv_dbg_if_jfifoTB.test.dut
  


  icarus
  coverage


 
 
 
 
 

adv_dbg_if_wb_tb
wb_tb

    PERIOD40
    TIMEOUT100000


  
  adv_dbg_if_wbTB.test.dut
  


  icarus
  coverage


 
 
 
 
 
 

adv_dbg_if_wb_cpu2_jsp_lint
wb_cpu2_jsp_lint

  rtl_check


 
 
 
 

adv_dbg_if_wb_cpu0_lint
wb_cpu0_lint

  rtl_check


 
 

adv_dbg_if_cpu0_lint
cpu0_lint

  rtl_check


 
 

adv_dbg_if_cpu1_lint
cpu1_lint

  rtl_check


 
 

adv_dbg_if_jsp_lint
jsp_lint

  rtl_check


 
 

adv_dbg_if_jfifo_lint
jfifo_lint

  rtl_check


 
 

adv_dbg_if_wb_lint
wb_lint

  rtl_check


 
 
 

 
 
 
 
 

 
   
       wb_cpu2_jsp
       adv_dbg_if_wb_cpu2_jsp_lint
    
 
 
   
       wb_cpu0
       adv_dbg_if_wb_cpu0_lint
    
 
 
 
   
       cpu0
       adv_dbg_if_cpu0_lint
    
 
 
   
       cpu1
       adv_dbg_if_cpu1_lint
    
 
 
 
   
       jsp
       adv_dbg_if_jsp_lint
    
 
   
       jfifo
       adv_dbg_if_jfifo_lint
    
 
 
   
       wb
       adv_dbg_if_wb_lint
    
 
 

 
 

 
 
 
 
 

cpu0
adv_dbg_if_cpu0_tb

 
 

cpu1
adv_dbg_if_cpu1_tb

 
 

jsp
adv_dbg_if_jsp_tb

 
 

jfifo
adv_dbg_if_jfifo_tb

 

jfifo_sync
adv_dbg_if_jfifo_sync_tb

 
 

jfifo_sync1
adv_dbg_if_jfifo_sync_tb

 
 
 

wb
adv_dbg_if_wb_tb

 
 
 
 

 
 
 
 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`adv_debug_sys`
12			`adv_dbg_if`
13
14
15
16			`2`
17			`_`
18			`_`
19			`_`
20			`VARIANT`
21	135	jt_eaton
22
23			`TestBenches`
24			`sim`
25			`testbenches`
26			`testbench`
27			`version`
28
29
30			`Fpgas`
31			`syn`
32			`ise`
33			`chip`
34			`variant`
35
36
37	131	jt_eaton
38	135	jt_eaton
39
40	131	jt_eaton
41
42			`/Hardware/adv_dbg_if/doc`
43
44
45
46
47
48
49
50			`adv_dbg_if/sim`
51
52
53
54
55
56
57
58
59			`adv_dbg_if_cpu0_tb`
60			`cpu0_tb`
61
62			`PERIOD40`
63			`TIMEOUT100000`
64
65
66
67			`adv_dbg_if_cpu0TB.test.dut`
68
69
70
71			`icarus`
72			`coverage`
73
74
75
76
77
78
79			`adv_dbg_if_cpu1_tb`
80			`cpu1_tb`
81
82			`PERIOD40`
83			`TIMEOUT100000`
84
85
86
87			`adv_dbg_if_cpu1TB.test.dut`
88
89
90
91			`icarus`
92			`coverage`
93
94
95
96
97
98
99
100
101
102			`adv_dbg_if_jsp_tb`
103			`jsp_tb`
104
105			`PERIOD40`
106			`TIMEOUT100000`
107
108
109
110			`adv_dbg_if_jspTB.test.dut`
111
112
113
114			`icarus`
115			`coverage`
116
117
118
119
120
121			`adv_dbg_if_jfifo_tb`
122			`jfifo_tb`
123
124			`PERIOD40`
125			`TIMEOUT100000`
126
127
128
129			`adv_dbg_if_jfifoTB.test.dut`
130
131
132
133			`icarus`
134			`coverage`
135
136
137
138
139
140
141			`adv_dbg_if_jfifo_sync_tb`
142			`jfifo_sync_tb`
143
144			`PERIOD40`
145			`TIMEOUT100000`
146
147
148
149			`adv_dbg_if_jfifoTB.test.dut`
150
151
152
153			`icarus`
154			`coverage`
155
156
157
158
159
160
161
162
163			`adv_dbg_if_wb_tb`
164			`wb_tb`
165
166			`PERIOD40`
167			`TIMEOUT100000`
168
169
170
171			`adv_dbg_if_wbTB.test.dut`
172
173
174
175			`icarus`
176			`coverage`
177
178
179
180
181
182
183
184
185
186			`adv_dbg_if_wb_cpu2_jsp_lint`
187			`wb_cpu2_jsp_lint`
188
189			`rtl_check`
190
191
192
193
194
195
196
197			`adv_dbg_if_wb_cpu0_lint`
198			`wb_cpu0_lint`
199
200			`rtl_check`
201
202
203
204
205
206			`adv_dbg_if_cpu0_lint`
207			`cpu0_lint`
208
209			`rtl_check`
210
211
212
213
214
215			`adv_dbg_if_cpu1_lint`
216			`cpu1_lint`
217
218			`rtl_check`
219
220
221
222
223
224			`adv_dbg_if_jsp_lint`
225			`jsp_lint`
226
227			`rtl_check`
228
229
230
231
232
233			`adv_dbg_if_jfifo_lint`
234			`jfifo_lint`
235
236			`rtl_check`
237
238
239
240
241
242			`adv_dbg_if_wb_lint`
243			`wb_lint`
244
245			`rtl_check`
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260			`wb_cpu2_jsp`
261			`adv_dbg_if_wb_cpu2_jsp_lint`
262
263
264
265
266			`wb_cpu0`
267			`adv_dbg_if_wb_cpu0_lint`
268
269
270
271
272
273			`cpu0`
274			`adv_dbg_if_cpu0_lint`
275
276
277
278
279			`cpu1`
280			`adv_dbg_if_cpu1_lint`
281
282
283
284
285
286			`jsp`
287			`adv_dbg_if_jsp_lint`
288
289
290
291			`jfifo`
292			`adv_dbg_if_jfifo_lint`
293
294
295
296
297			`wb`
298			`adv_dbg_if_wb_lint`
299
300
301
302
303
304
305
306
307
308
309
310
311
312			`cpu0`
313			`adv_dbg_if_cpu0_tb`
314
315
316
317
318			`cpu1`
319			`adv_dbg_if_cpu1_tb`
320
321
322
323
324			`jsp`
325			`adv_dbg_if_jsp_tb`
326
327
328
329
330			`jfifo`
331			`adv_dbg_if_jfifo_tb`
332
333
334
335			`jfifo_sync`
336			`adv_dbg_if_jfifo_sync_tb`
337
338
339
340
341			`jfifo_sync1`
342			`adv_dbg_if_jfifo_sync_tb`
343
344
345
346
347
348			`wb`
349			`adv_dbg_if_wb_tb`
350
351
352
353
354
355
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363
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365