URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [doc/] [sch/] [adv_dbg_if_jfifo.sch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20100214 1`
2			`C 1900 300 1 0 0 in_port_vector.sym`
3			`{`
4			`T 1900 300 5 10 1 1 0 6 1 1`
5			`refdes=wb_jsp_dat_i[7:0]`
6			`}`
7			`C 1900 700 1 0 0 in_port.sym`
8			`{`
9			`T 1900 700 5 10 1 1 0 6 1 1`
10			`refdes=wb_jsp_stb_i`
11			`}`
12			`C 1900 1100 1 0 0 in_port.sym`
13			`{`
14			`T 1900 1100 5 10 1 1 0 6 1 1`
15			`refdes=wb_clk_i`
16			`}`
17			`C 1900 1500 1 0 0 in_port.sym`
18			`{`
19			`T 1900 1500 5 10 1 1 0 6 1 1`
20			`refdes=update_dr_i`
21			`}`
22			`C 1900 1900 1 0 0 in_port.sym`
23			`{`
24			`T 1900 1900 5 10 1 1 0 6 1 1`
25			`refdes=tdi_i`
26			`}`
27			`C 1900 2300 1 0 0 in_port.sym`
28			`{`
29			`T 1900 2300 5 10 1 1 0 6 1 1`
30			`refdes=tck_i`
31			`}`
32			`C 1900 2700 1 0 0 in_port.sym`
33			`{`
34			`T 1900 2700 5 10 1 1 0 6 1 1`
35			`refdes=shift_dr_i`
36			`}`
37			`C 1900 3100 1 0 0 in_port.sym`
38			`{`
39			`T 1900 3100 5 10 1 1 0 6 1 1`
40			`refdes=rst_i`
41			`}`
42			`C 1900 3500 1 0 0 in_port.sym`
43			`{`
44			`T 1900 3500 5 10 1 1 0 6 1 1`
45			`refdes=debug_select_i`
46			`}`
47			`C 1900 3900 1 0 0 in_port.sym`
48			`{`
49			`T 1900 3900 5 10 1 1 0 6 1 1`
50			`refdes=capture_dr_i`
51			`}`
52			`C 4900 300 1 0 0 out_port_vector.sym`
53			`{`
54			`T 5900 300 5 10 1 1 0 0 1 1`
55			`refdes=jsp_data_out[7:0]`
56			`}`
57			`C 4900 700 1 0 0 out_port.sym`
58			`{`
59			`T 5900 700 5 10 1 1 0 0 1 1`
60			`refdes=tdo_o`
61			`}`
62			`C 4900 1100 1 0 0 out_port.sym`
63			`{`
64			`T 5900 1100 5 10 1 1 0 0 1 1`
65			`refdes=biu_wr_strobe`
66			`}`