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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [doc/] [sch/] [adv_dbg_if_jsp.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2000 300 1 0 0 in_port_vector.sym
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{
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T 2000 300 5 10 1 1 0 6 1 1
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refdes=wb_jsp_sel_i[3:0]
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}
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C 2000 700 1 0 0 in_port_vector.sym
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{
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T 2000 700 5 10 1 1 0 6 1 1
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refdes=wb_jsp_dat_i[31:0]
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}
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C 2000 1100 1 0 0 in_port_vector.sym
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{
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T 2000 1100 5 10 1 1 0 6 1 1
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refdes=wb_jsp_cti_i[2:0]
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}
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C 2000 1500 1 0 0 in_port_vector.sym
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{
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T 2000 1500 5 10 1 1 0 6 1 1
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refdes=wb_jsp_bte_i[1:0]
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}
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C 2000 1900 1 0 0 in_port_vector.sym
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{
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T 2000 1900 5 10 1 1 0 6 1 1
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refdes=wb_jsp_adr_i[31:0]
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}
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C 2000 2300 1 0 0 in_port.sym
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{
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T 2000 2300 5 10 1 1 0 6 1 1
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refdes=wb_rst_i
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}
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C 2000 2700 1 0 0 in_port.sym
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{
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T 2000 2700 5 10 1 1 0 6 1 1
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refdes=wb_jsp_we_i
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}
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C 2000 3100 1 0 0 in_port.sym
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{
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T 2000 3100 5 10 1 1 0 6 1 1
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refdes=wb_jsp_stb_i
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}
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C 2000 3500 1 0 0 in_port.sym
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{
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T 2000 3500 5 10 1 1 0 6 1 1
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refdes=wb_jsp_cyc_i
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}
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C 2000 3900 1 0 0 in_port.sym
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{
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T 2000 3900 5 10 1 1 0 6 1 1
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refdes=wb_jsp_cab_i
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}
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C 2000 4300 1 0 0 in_port.sym
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{
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T 2000 4300 5 10 1 1 0 6 1 1
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refdes=wb_clk_i
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}
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C 2000 4700 1 0 0 in_port.sym
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{
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T 2000 4700 5 10 1 1 0 6 1 1
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refdes=update_dr_i
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}
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C 2000 5100 1 0 0 in_port.sym
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{
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T 2000 5100 5 10 1 1 0 6 1 1
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refdes=tdi_i
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}
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C 2000 5500 1 0 0 in_port.sym
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{
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T 2000 5500 5 10 1 1 0 6 1 1
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refdes=tck_i
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}
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C 2000 5900 1 0 0 in_port.sym
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{
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T 2000 5900 5 10 1 1 0 6 1 1
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refdes=shift_dr_i
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}
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C 2000 6300 1 0 0 in_port.sym
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{
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T 2000 6300 5 10 1 1 0 6 1 1
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refdes=rst_i
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}
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C 2000 6700 1 0 0 in_port.sym
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{
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T 2000 6700 5 10 1 1 0 6 1 1
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refdes=debug_select_i
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}
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C 2000 7100 1 0 0 in_port.sym
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{
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T 2000 7100 5 10 1 1 0 6 1 1
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refdes=capture_dr_i
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}
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C 5100 300  1 0  0 out_port_vector.sym
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{
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T 6100 300 5  10 1 1 0 0 1 1
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refdes=wb_jsp_dat_o[31:0]
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}
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C 5100 700  1 0  0 out_port_vector.sym
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{
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T 6100 700 5  10 1 1 0 0 1 1
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refdes=jsp_data_out[7:0]
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}
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C 5100 1100  1 0 0 out_port.sym
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{
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T 6100 1100 5  10 1 1 0 0 1 1
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refdes=wb_jsp_err_o
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}
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C 5100 1500  1 0 0 out_port.sym
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{
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T 6100 1500 5  10 1 1 0 0 1 1
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refdes=wb_jsp_ack_o
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}
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C 5100 1900  1 0 0 out_port.sym
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{
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T 6100 1900 5  10 1 1 0 0 1 1
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refdes=tdo_o
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}
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C 5100 2300  1 0 0 out_port.sym
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{
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T 6100 2300 5  10 1 1 0 0 1 1
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refdes=int_o
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}
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C 5100 2700  1 0 0 out_port.sym
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{
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T 6100 2700 5  10 1 1 0 0 1 1
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refdes=biu_wr_strobe
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}

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