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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [doc/] [sch/] [adv_dbg_if_wb_cpu0.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
C 1900 300 1 0 0 in_port_vector.sym
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{
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T 1900 300 5 10 1 1 0 6 1 1
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refdes=wb_dat_i[31:0]
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}
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C 1900 700 1 0 0 in_port_vector.sym
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{
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T 1900 700 5 10 1 1 0 6 1 1
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refdes=cpu0_data_i[31:0]
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}
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C 1900 1100 1 0 0 in_port.sym
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{
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T 1900 1100 5 10 1 1 0 6 1 1
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refdes=wb_rst_i
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}
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C 1900 1500 1 0 0 in_port.sym
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{
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T 1900 1500 5 10 1 1 0 6 1 1
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refdes=wb_err_i
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}
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C 1900 1900 1 0 0 in_port.sym
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{
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T 1900 1900 5 10 1 1 0 6 1 1
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refdes=wb_clk_i
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}
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C 1900 2300 1 0 0 in_port.sym
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{
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T 1900 2300 5 10 1 1 0 6 1 1
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refdes=wb_ack_i
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}
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C 1900 2700 1 0 0 in_port.sym
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{
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T 1900 2700 5 10 1 1 0 6 1 1
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refdes=update_dr_i
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}
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C 1900 3100 1 0 0 in_port.sym
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{
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T 1900 3100 5 10 1 1 0 6 1 1
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refdes=tdi_i
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}
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C 1900 3500 1 0 0 in_port.sym
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{
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T 1900 3500 5 10 1 1 0 6 1 1
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refdes=tck_i
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}
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C 1900 3900 1 0 0 in_port.sym
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{
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T 1900 3900 5 10 1 1 0 6 1 1
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refdes=shift_dr_i
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}
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C 1900 4300 1 0 0 in_port.sym
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{
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T 1900 4300 5 10 1 1 0 6 1 1
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refdes=rst_i
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}
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C 1900 4700 1 0 0 in_port.sym
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{
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T 1900 4700 5 10 1 1 0 6 1 1
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refdes=debug_select_i
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}
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C 1900 5100 1 0 0 in_port.sym
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{
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T 1900 5100 5 10 1 1 0 6 1 1
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refdes=cpu0_clk_i
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}
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C 1900 5500 1 0 0 in_port.sym
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{
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T 1900 5500 5 10 1 1 0 6 1 1
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refdes=cpu0_bp_i
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}
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C 1900 5900 1 0 0 in_port.sym
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{
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T 1900 5900 5 10 1 1 0 6 1 1
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refdes=cpu0_ack_i
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}
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C 1900 6300 1 0 0 in_port.sym
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{
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T 1900 6300 5 10 1 1 0 6 1 1
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refdes=capture_dr_i
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}
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C 4900 300  1 0  0 out_port_vector.sym
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{
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T 5900 300 5  10 1 1 0 0 1 1
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refdes=wb_sel_o[3:0]
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}
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C 4900 700  1 0  0 out_port_vector.sym
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{
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T 5900 700 5  10 1 1 0 0 1 1
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refdes=wb_dat_o[31:0]
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}
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C 4900 1100  1 0  0 out_port_vector.sym
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{
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T 5900 1100 5  10 1 1 0 0 1 1
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refdes=wb_cti_o[2:0]
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}
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C 4900 1500  1 0  0 out_port_vector.sym
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{
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T 5900 1500 5  10 1 1 0 0 1 1
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refdes=wb_bte_o[1:0]
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}
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C 4900 1900  1 0  0 out_port_vector.sym
103 
{
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T 5900 1900 5  10 1 1 0 0 1 1
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refdes=wb_adr_o[31:0]
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}
107 
C 4900 2300  1 0  0 out_port_vector.sym
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{
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T 5900 2300 5  10 1 1 0 0 1 1
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refdes=cpu0_data_o[31:0]
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}
112 
C 4900 2700  1 0  0 out_port_vector.sym
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{
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T 5900 2700 5  10 1 1 0 0 1 1
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refdes=cpu0_addr_o[31:0]
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}
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C 4900 3100  1 0 0 out_port.sym
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{
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T 5900 3100 5  10 1 1 0 0 1 1
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refdes=wb_we_o
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}
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C 4900 3500  1 0 0 out_port.sym
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{
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T 5900 3500 5  10 1 1 0 0 1 1
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refdes=wb_stb_o
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}
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C 4900 3900  1 0 0 out_port.sym
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{
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T 5900 3900 5  10 1 1 0 0 1 1
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refdes=wb_cyc_o
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}
132 
C 4900 4300  1 0 0 out_port.sym
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{
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T 5900 4300 5  10 1 1 0 0 1 1
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refdes=wb_cab_o
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}
137 
C 4900 4700  1 0 0 out_port.sym
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{
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T 5900 4700 5  10 1 1 0 0 1 1
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refdes=tdo_o
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}
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C 4900 5100  1 0 0 out_port.sym
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{
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T 5900 5100 5  10 1 1 0 0 1 1
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refdes=cpu0_we_o
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}
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C 4900 5500  1 0 0 out_port.sym
148 
{
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T 5900 5500 5  10 1 1 0 0 1 1
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refdes=cpu0_stb_o
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}
152 
C 4900 5900  1 0 0 out_port.sym
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{
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T 5900 5900 5  10 1 1 0 0 1 1
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refdes=cpu0_stall_o
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}
157 
C 4900 6300  1 0 0 out_port.sym
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{
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T 5900 6300 5  10 1 1 0 0 1 1
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refdes=cpu0_rst_o
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}

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