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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb
 

 

  gen_verilog
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      wb
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        wb_biu
        ../verilog/adbg_wb_biu.v
        verilogSource
        module
      
 
      
        wb_module
        ../verilog/adbg_wb_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="jtag_i"/>
              
              
 
 
              
              wb
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="wb_i"/>
              
              
 
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`wb`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton
45			`gen_verilog`
46			`104.0`
47			`none`
48			`:Simulation:`
49			`tools/verilog/gen_verilog`
50
51
52			`destination`
53			`wb`
54
55
56
57	131	jt_eaton
58
59
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61
62
63
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65
66	135	jt_eaton
67	131	jt_eaton
68
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72	135	jt_eaton
73	131	jt_eaton
74
75
76	135	jt_eaton
77			`fs-sim`
78	131	jt_eaton
79	135	jt_eaton
80
81			`../verilog/wb_defines.v`
82			`verilogSource`
83			`include`
84
85	131	jt_eaton
86	135	jt_eaton
87
88			`../verilog/adbg_wb_defines.v`
89			`verilogSource`
90			`include`
91
92	131	jt_eaton
93	135	jt_eaton
94
95			`../verilog/adbg_top.v`
96			`verilogSource`
97			`module`
98
99	131	jt_eaton
100	135	jt_eaton
101			`crc32`
102			`../verilog/adbg_crc32.v`
103			`verilogSource`
104			`module`
105
106	131	jt_eaton
107	135	jt_eaton
108			`wb_biu`
109			`../verilog/adbg_wb_biu.v`
110			`verilogSource`
111			`module`
112
113	131	jt_eaton
114	135	jt_eaton
115			`wb_module`
116			`../verilog/adbg_wb_module.v`
117			`verilogSource`
118			`module`
119
120	131	jt_eaton
121
122	135	jt_eaton
123			`bytefifo`
124			`../verilog/adbg_bytefifo.v`
125			`verilogSource`
126			`module`
127
128	131	jt_eaton
129	135	jt_eaton
130			`syncflop`
131			`../verilog/adbg_syncflop.v`
132			`verilogSource`
133			`module`
134
135	131	jt_eaton
136	135	jt_eaton
137			`syncreg`
138			`../verilog/adbg_syncreg.v`
139			`verilogSource`
140			`module`
141
142	131	jt_eaton
143
144
145	135	jt_eaton
146	131	jt_eaton
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152
153
154	135	jt_eaton
155
156	131	jt_eaton
157
158	135	jt_eaton
159			`jtag`
160
161
162			`ipxact:library="adv_debug_sys"`
163			`ipxact:name="adv_dbg_if"`
164			`ipxact:version="jtag_i"/>`
165
166
167	131	jt_eaton
168
169	135	jt_eaton
170			`wb`
171
172
173			`ipxact:library="adv_debug_sys"`
174			`ipxact:name="adv_dbg_if"`
175			`ipxact:version="wb_i"/>`
176
177
178	131	jt_eaton
179
180
181	135	jt_eaton
182			`verilog`
183
184
185			`ipxact:library="Testbench"`
186			`ipxact:name="toolflow"`
187			`ipxact:version="verilog"/>`
188
189
190	131	jt_eaton
191
192
193
194
195
196	135	jt_eaton
197			`sim:Simulation:`
198			`Verilog`
199
200
201			`fs-sim`
202
203
204	131	jt_eaton
205
206	135	jt_eaton
207			`syn:Synthesis:`
208			`Verilog`
209
210
211			`fs-sim`
212
213
214	131	jt_eaton
215	135	jt_eaton
216			`doc`
217
218
219			`ipxact:library="Testbench"`
220			`ipxact:name="toolflow"`
221			`ipxact:version="documentation"/>`
222
223			`:Documentation:`
224			`Verilog`
225
226	131	jt_eaton
227
228
229	135	jt_eaton
230	131	jt_eaton
231
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251	135	jt_eaton