Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

adv_debug_sys

adv_dbg_if

wb_cpu0_jfifo

  gen_verilog

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      wb_cpu0_jfifo

      fs-sim

        ../verilog/wb_cpu0_jfifo_defines.v

        verilogSource

        include

        ../verilog/adbg_or1k_defines.v

        verilogSource

        include

        ../verilog/adbg_wb_defines.v

        verilogSource

        include

        ../verilog/adbg_wb_cpu0_jfifo.v

        verilogSource

        module

        crc32

        ../verilog/adbg_crc32.v

        verilogSource

        module

        jfifo_biu

        ../verilog/adbg_jfifo_biu.v

        verilogSource

        module

        jfifo_module

        ../verilog/adbg_jfifo_module.v

        verilogSource

        module

        or1k_biu

        ../verilog/adbg_or1k_biu.v

        verilogSource

        module

        or1k_module

        ../verilog/adbg_or1k_module.v

        verilogSource

        module

        or1k_status_reg

        ../verilog/adbg_or1k_status_reg.v

        verilogSource

        module

        wb_biu

        ../verilog/adbg_wb_biu.v

        verilogSource

        module

        wb_module

        ../verilog/adbg_wb_module.v

        verilogSource

        module

        bytefifo

        ../verilog/adbg_bytefifo.v

        verilogSource

        module

        syncflop

        ../verilog/adbg_syncflop.v

        verilogSource

        module

        syncreg

        ../verilog/adbg_syncreg.v

        verilogSource

        module

      fs-syn

        ../verilog/SYNTHESIS

        verilogSource

        include

        ../verilog/wb_cpu0_jfifo_defines.v

        verilogSource

        include

        ../verilog/adbg_or1k_defines.v

        verilogSource

        include

        ../verilog/adbg_wb_defines.v

        verilogSource

        include

        ../verilog/adbg_wb_cpu0_jfifo.v

        verilogSource

        module

        crc32

        ../verilog/adbg_crc32.v

        verilogSource

        module

        jfifo_biu

        ../verilog/adbg_jfifo_biu.v

        verilogSource

        module

        jfifo_module

        ../verilog/adbg_jfifo_module.v

        verilogSource

        module

        or1k_biu

        ../verilog/adbg_or1k_biu.v

        verilogSource

        module

        or1k_module

        ../verilog/adbg_or1k_module.v

        verilogSource

        module

        or1k_status_reg

        ../verilog/adbg_or1k_status_reg.v

        verilogSource

        module

        wb_biu

        ../verilog/adbg_wb_biu.v

        verilogSource

        module

        wb_module

        ../verilog/adbg_wb_module.v

        verilogSource

        module

        bytefifo

        ../verilog/adbg_bytefifo.v

        verilogSource

        module

        syncflop

        ../verilog/adbg_syncflop.v

        verilogSource

        module

        syncreg

        ../verilog/adbg_syncreg.v

        verilogSource

        module

              jtag

                                   ipxact:library="adv_debug_sys"

                                   ipxact:name="adv_dbg_if"

                                   ipxact:version="jtag_i"/>

              cpu0

                                   ipxact:library="adv_debug_sys"

                                   ipxact:name="adv_dbg_if"

                                   ipxact:version="cpu0_i"/>

              wb

                                   ipxact:library="adv_debug_sys"

                                   ipxact:name="adv_dbg_if"

                                   ipxact:version="wb_i"/>

              jfifo

                                   ipxact:library="adv_debug_sys"

                                   ipxact:name="adv_dbg_if"

                                   ipxact:version="jfifo_i"/>

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

int_o

wire

out

biu_wr_strobe

wire

out

jsp_data_out

reg

out70