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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu0_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
cpu0_lint
 
 
 
 
 

 
 
     
 
              
              Dut
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="cpu0_dut.params"/>
              
              
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 

 
 

 
   
      fs-lint
 
      
        
        ../verilog/lint/adv_dbg_if_cpu0_lint
        verilogSource
        module
      
 
    
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`cpu0_lint`
41	131	jt_eaton
42	133	jt_eaton
43
44
45
46	135	jt_eaton
47	131	jt_eaton
48
49	135	jt_eaton
50	131	jt_eaton
51	135	jt_eaton
52			`Dut`
53
54
55			`ipxact:library="adv_debug_sys"`
56			`ipxact:name="adv_dbg_if"`
57			`ipxact:version="cpu0_dut.params"/>`
58
59
60	131	jt_eaton
61	135	jt_eaton
62			`lint`
63			`:Lint:`
64			`Verilog`
65			`fs-lint`
66
67	131	jt_eaton
68	135	jt_eaton
69			`rtl_check`
70
71
72			`ipxact:library="Testbench"`
73			`ipxact:name="toolflow"`
74			`ipxact:version="rtl_check"/>`
75
76
77	131	jt_eaton
78	135	jt_eaton
79	131	jt_eaton
80
81	135	jt_eaton
82	131	jt_eaton
83
84	135	jt_eaton
85	131	jt_eaton
86	135	jt_eaton
87			`fs-lint`
88	131	jt_eaton
89	135	jt_eaton
90
91			`../verilog/lint/adv_dbg_if_cpu0_lint`
92			`verilogSource`
93			`module`
94
95	131	jt_eaton
96	135	jt_eaton
97	131	jt_eaton
98	135	jt_eaton
99	131	jt_eaton
100	135	jt_eaton
101	131	jt_eaton
102
103
104
105
106

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu0_lint.xml] - Blame information for rev 135