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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu1_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
cpu1_lint
 
 
 
 
 
 

 
 
     
 
              
              Dut
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="cpu1_dut.params"/>
              
              
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 

 
 

 
   
      fs-lint
 
      
        
        ../verilog/lint/adv_dbg_if_cpu1_lint
        verilogSource
        module
      
 
    
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`cpu1_lint`
41	131	jt_eaton
42	133	jt_eaton
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50	135	jt_eaton
51	131	jt_eaton
52	135	jt_eaton
53			`Dut`
54
55
56			`ipxact:library="adv_debug_sys"`
57			`ipxact:name="adv_dbg_if"`
58			`ipxact:version="cpu1_dut.params"/>`
59
60
61	131	jt_eaton
62	135	jt_eaton
63			`lint`
64			`:Lint:`
65			`Verilog`
66			`fs-lint`
67
68	131	jt_eaton
69	135	jt_eaton
70			`rtl_check`
71
72
73			`ipxact:library="Testbench"`
74			`ipxact:name="toolflow"`
75			`ipxact:version="rtl_check"/>`
76
77
78	131	jt_eaton
79	135	jt_eaton
80	131	jt_eaton
81
82	135	jt_eaton
83	131	jt_eaton
84
85	135	jt_eaton
86	131	jt_eaton
87	135	jt_eaton
88			`fs-lint`
89	131	jt_eaton
90	135	jt_eaton
91
92			`../verilog/lint/adv_dbg_if_cpu1_lint`
93			`verilogSource`
94			`module`
95
96	131	jt_eaton
97	135	jt_eaton
98	131	jt_eaton
99	135	jt_eaton
100	131	jt_eaton
101	135	jt_eaton
102	131	jt_eaton
103
104
105
106
107

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu1_lint.xml] - Blame information for rev 135