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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_cpu0_duth.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
adv_debug_sys
adv_dbg_if
wb_cpu0_duth.design

 

capture_dr_i



 

cpu0_ack_i



 

cpu0_addr_o



 

cpu0_bp_i



 

cpu0_clk_i



 

cpu0_data_i



 

cpu0_data_o



 

cpu0_rst_o



 

cpu0_stall_o



 

cpu0_stb_o



 

cpu0_we_o



 

debug_select_i



 

rst_i



 

shift_dr_i



 

tck_i



 

tdi_i



 

tdo_o



 

update_dr_i



 

wb_ack_i



 

wb_adr_o



 

wb_bte_o



 

wb_cab_o



 

wb_clk_i



 

wb_cti_o



 

wb_cyc_o



 

wb_dat_i



 

wb_dat_o



 

wb_err_i



 

wb_rst_i



 

wb_sel_o



 

wb_stb_o



 

wb_we_o



 
 


 

dut







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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_cpu0_duth.design.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	133	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`adv_debug_sys`
17			`adv_dbg_if`
18			`wb_cpu0_duth.design`
19
20	133	jt_eaton
21	135	jt_eaton
22			`capture_dr_i`
23
24
25
26	133	jt_eaton
27	135	jt_eaton
28			`cpu0_ack_i`
29
30
31
32	133	jt_eaton
33	135	jt_eaton
34			`cpu0_addr_o`
35
36
37
38	133	jt_eaton
39	135	jt_eaton
40			`cpu0_bp_i`
41
42
43
44	133	jt_eaton
45	135	jt_eaton
46			`cpu0_clk_i`
47
48
49
50	133	jt_eaton
51	135	jt_eaton
52			`cpu0_data_i`
53
54
55
56	133	jt_eaton
57	135	jt_eaton
58			`cpu0_data_o`
59
60
61
62	133	jt_eaton
63	135	jt_eaton
64			`cpu0_rst_o`
65
66
67
68	133	jt_eaton
69	135	jt_eaton
70			`cpu0_stall_o`
71
72
73
74	133	jt_eaton
75	135	jt_eaton
76			`cpu0_stb_o`
77
78
79
80	133	jt_eaton
81	135	jt_eaton
82			`cpu0_we_o`
83
84
85
86	133	jt_eaton
87	135	jt_eaton
88			`debug_select_i`
89
90
91
92	133	jt_eaton
93	135	jt_eaton
94			`rst_i`
95
96
97
98	133	jt_eaton
99	135	jt_eaton
100			`shift_dr_i`
101
102
103
104	133	jt_eaton
105	135	jt_eaton
106			`tck_i`
107
108
109
110	133	jt_eaton
111	135	jt_eaton
112			`tdi_i`
113
114
115
116	133	jt_eaton
117	135	jt_eaton
118			`tdo_o`
119
120
121
122	133	jt_eaton
123	135	jt_eaton
124			`update_dr_i`
125
126
127
128	133	jt_eaton
129	135	jt_eaton
130			`wb_ack_i`
131
132
133
134	133	jt_eaton
135	135	jt_eaton
136			`wb_adr_o`
137
138
139
140	133	jt_eaton
141	135	jt_eaton
142			`wb_bte_o`
143
144
145
146	133	jt_eaton
147	135	jt_eaton
148			`wb_cab_o`
149
150
151
152	133	jt_eaton
153	135	jt_eaton
154			`wb_clk_i`
155
156
157
158	133	jt_eaton
159	135	jt_eaton
160			`wb_cti_o`
161
162
163
164	133	jt_eaton
165	135	jt_eaton
166			`wb_cyc_o`
167
168
169
170	133	jt_eaton
171	135	jt_eaton
172			`wb_dat_i`
173
174
175
176	133	jt_eaton
177	135	jt_eaton
178			`wb_dat_o`
179
180
181
182	133	jt_eaton
183	135	jt_eaton
184			`wb_err_i`
185
186
187
188	133	jt_eaton
189	135	jt_eaton
190			`wb_rst_i`
191
192
193
194	133	jt_eaton
195	135	jt_eaton
196			`wb_sel_o`
197
198
199
200	133	jt_eaton
201	135	jt_eaton
202			`wb_stb_o`
203
204
205
206	133	jt_eaton
207	135	jt_eaton
208			`wb_we_o`
209
210
211
212	133	jt_eaton
213
214	135	jt_eaton
215
216	133	jt_eaton
217	135	jt_eaton
218			`dut`
219
220
221
222
223
224