URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_cpu0_lint.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb_cpu0_lint
 
 
 
 

 
 
     
 
              
              Dut
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="wb_cpu0_dut.params"/>
              
              
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 

 
 

 
   
      fs-lint
 
      
        
        ../verilog/lint/adv_dbg_if_wb_cpu0_lint
        verilogSource
        module
      
 
    
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`wb_cpu0_lint`
41	131	jt_eaton
42	133	jt_eaton
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton
49	131	jt_eaton
50	135	jt_eaton
51			`Dut`
52
53
54			`ipxact:library="adv_debug_sys"`
55			`ipxact:name="adv_dbg_if"`
56			`ipxact:version="wb_cpu0_dut.params"/>`
57
58
59	131	jt_eaton
60	135	jt_eaton
61			`lint`
62			`:Lint:`
63			`Verilog`
64			`fs-lint`
65
66	131	jt_eaton
67	135	jt_eaton
68			`rtl_check`
69
70
71			`ipxact:library="Testbench"`
72			`ipxact:name="toolflow"`
73			`ipxact:version="rtl_check"/>`
74
75
76	131	jt_eaton
77	135	jt_eaton
78	131	jt_eaton
79
80	135	jt_eaton
81	131	jt_eaton
82
83	135	jt_eaton
84	131	jt_eaton
85	135	jt_eaton
86			`fs-lint`
87	131	jt_eaton
88	135	jt_eaton
89
90			`../verilog/lint/adv_dbg_if_wb_cpu0_lint`
91			`verilogSource`
92			`module`
93
94	131	jt_eaton
95	135	jt_eaton
96	131	jt_eaton
97	135	jt_eaton
98	131	jt_eaton
99	135	jt_eaton
100	131	jt_eaton
101
102
103
104
105

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_cpu0_lint.xml] - Blame information for rev 135