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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      adv_dbg_if_wb_tb
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4
    wb_addr_width         32
    wb_data_width         32
    wb_byte_lanes         4

 
       
 
              
              Params
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="wb_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              wb_Bfm
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="wb_bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
 
 
   
      fs-common
 
 
      
        
        ../verilog/tb.wb
        verilogSource
        fragment
      
 
 
 
 
 
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/tb.ext
        verilogSource
        fragment
      
 
 
 
 
      
        
        ../verilog/common/adv_dbg_if_wb_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/adv_dbg_if_wb_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`adv_debug_sys`
14			`adv_dbg_if`
15			`wb_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`adv_dbg_if_wb_tb`
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50			`JTAG_MODEL_DIVCNT 4'h4`
51			`JTAG_MODEL_SIZE 4`
52			`wb_addr_width 32`
53			`wb_data_width 32`
54			`wb_byte_lanes 4`
55
56	131	jt_eaton
57	135	jt_eaton
58	131	jt_eaton
59	135	jt_eaton
60			`Params`
61
62
63			`ipxact:library="adv_debug_sys"`
64			`ipxact:name="adv_dbg_if"`
65			`ipxact:version="wb_dut.params"/>`
66
67
68	131	jt_eaton
69
70	135	jt_eaton
71			`Bfm`
72
73			`ipxact:library="adv_debug_sys"`
74			`ipxact:name="adv_dbg_if"`
75			`ipxact:version="bfm.design"/>`
76
77	131	jt_eaton
78
79	135	jt_eaton
80			`wb_Bfm`
81
82			`ipxact:library="adv_debug_sys"`
83			`ipxact:name="adv_dbg_if"`
84			`ipxact:version="wb_bfm.design"/>`
85
86	131	jt_eaton
87
88	135	jt_eaton
89			`icarus`
90
91
92			`ipxact:library="Testbench"`
93			`ipxact:name="toolflow"`
94			`ipxact:version="icarus"/>`
95
96
97	131	jt_eaton
98
99
100
101	135	jt_eaton
102			`common:common:`
103			`Verilog`
104
105
106			`fs-common`
107
108
109	131	jt_eaton
110
111	135	jt_eaton
112			`sim:Simulation:`
113			`Verilog`
114
115
116			`fs-sim`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`lint:Lint:`
122			`Verilog`
123
124
125			`fs-lint`
126
127
128	131	jt_eaton
129	135	jt_eaton
130	131	jt_eaton
131
132
133
134	135	jt_eaton
135	131	jt_eaton
136
137
138
139
140	135	jt_eaton
141	131	jt_eaton
142
143
144
145	135	jt_eaton
146			`fs-common`
147	131	jt_eaton
148
149	135	jt_eaton
150
151			`../verilog/tb.wb`
152			`verilogSource`
153			`fragment`
154
155	131	jt_eaton
156
157
158
159
160
161
162
163	135	jt_eaton
164	131	jt_eaton
165
166
167
168
169	135	jt_eaton
170			`fs-sim`
171	131	jt_eaton
172
173	135	jt_eaton
174
175			`../verilog/tb.ext`
176			`verilogSource`
177			`fragment`
178
179	131	jt_eaton
180
181
182
183	135	jt_eaton
184
185			`../verilog/common/adv_dbg_if_wb_tb`
186			`verilogSourcemodule`
187
188	131	jt_eaton
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195	135	jt_eaton
196			`fs-lint`
197
198
199			`../verilog/common/adv_dbg_if_wb_tb`
200			`verilogSourcemodule`
201
202	131	jt_eaton
203
204	135	jt_eaton
205	131	jt_eaton
206
207
208
209
210	135	jt_eaton
211	131	jt_eaton
212
213
214
215
216	135	jt_eaton