Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

fpgas

Nexys2_T6502

core

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      Nexys2_T6502_core

                                Hierarchical

                Hierarchical:*Simulation:*

   Hierarchical

              Core:*Simulation:*

                                   ipxact:library="Nexys2"

                                   ipxact:name="fpga"

                                   ipxact:version="core"/>

              verilog:*Simulation:*

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              common:*common:*

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-sim

      fs-common

        ../verilog/top.jabc

        verilogSourcefragment

        ../verilog/top.gpio

        verilogSourcefragment

        ../verilog/top.rs_uart

        verilogSourcefragment

        ../verilog

        verilogSourcelibraryDir

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/Nexys2_T6502_core

        verilogSourcemodule