URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [verilog/] [sram.load] - Blame information for rev 135

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parameter PREFIX ="../../../../../../../code/";
 
initial
   begin
   if(      STARTUP  != "NONE") begin  $readmemh( {PREFIX,STARTUP}       ,dut.core.T6502.io_module.vga.vga_char_ctrl.char_ram.mem);end
   if(         FONT  != "NONE") begin  $readmemh( {PREFIX,FONT}          ,dut.core.T6502.io_module.vga.vga_char_ctrl.char_gen_rom.mem);end
   if(PROG_ROM_FILE  != "NONE") begin  $readmemh( {PREFIX,PROG_ROM_FILE} ,dut.core.T6502.cpu.prog_rom.mem);end
   if(PROG_ROM_FILE  != "NONE") begin  $readmemh( {PREFIX,PROG_ROM_FILE} ,dut.core.T6502.sh_prog_rom.mem );end
   if(     ROM_FILE  != "NONE") begin  $readmemh( {PREFIX,ROM_FILE}      ,dut.core.T6502.boot_rom.mem);end
   end
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`parameter PREFIX ="../../../../../../../code/";`
2	131	jt_eaton
3			`initial`
4			`begin`
5			`if( STARTUP != "NONE") begin $readmemh( {PREFIX,STARTUP} ,dut.core.T6502.io_module.vga.vga_char_ctrl.char_ram.mem);end`
6	134	jt_eaton	`if( FONT != "NONE") begin $readmemh( {PREFIX,FONT} ,dut.core.T6502.io_module.vga.vga_char_ctrl.char_gen_rom.mem);end`
7	131	jt_eaton	`if(PROG_ROM_FILE != "NONE") begin $readmemh( {PREFIX,PROG_ROM_FILE} ,dut.core.T6502.cpu.prog_rom.mem);end`
8			`if(PROG_ROM_FILE != "NONE") begin $readmemh( {PREFIX,PROG_ROM_FILE} ,dut.core.T6502.sh_prog_rom.mem );end`
9			`if( ROM_FILE != "NONE") begin $readmemh( {PREFIX,ROM_FILE} ,dut.core.T6502.boot_rom.mem);end`
10			`end`
11
12

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [verilog/] [sram.load] - Blame information for rev 135