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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_dut.params.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default_dut.params

 
      
 
              
              Dut
 
              
                                   ipxact:library="fpgas"
                                   ipxact:name="Nexys2_T6502"
                                   ipxact:version="default_duth.design"/>
              
      

    RAM_WORDS2048
    RAM_ADD11
    ROM_WORDS128
    ROM_ADD7
    ROM_FILE"NONE"
    PROG_ROM_FILE"NONE"
    PROG_ROM_WORDS128
    PROG_ROM_ADD7
    VEC_TABLE8'hff
    STARTUP"NONE"
    FONT"NONE"
    CLOCK_FREQ50
    CLOCK_PLL_MULT2
    CLOCK_PLL_DIV4
    CLOCK_PLL_SIZE4
    CLOCK_SRC0
    RESET_SENSE0
    UART_PRESCALE5'b01100
    UART_PRE_SIZE5
    UART_DIV0
    JTAG_USER1_WIDTH8
    JTAG_USER1_RESET8'h12




Line No.	Rev	Author	Line
1	131	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`fpgas`
17			`Nexys2_T6502`
18			`default_dut.params`
19
20	131	jt_eaton
21	135	jt_eaton
22	131	jt_eaton
23	135	jt_eaton
24			`Dut`
25	131	jt_eaton
26	135	jt_eaton
27			`ipxact:library="fpgas"`
28			`ipxact:name="Nexys2_T6502"`
29			`ipxact:version="default_duth.design"/>`
30
31
32
33			`RAM_WORDS2048`
34			`RAM_ADD11`
35			`ROM_WORDS128`
36			`ROM_ADD7`
37			`ROM_FILE"NONE"`
38			`PROG_ROM_FILE"NONE"`
39			`PROG_ROM_WORDS128`
40			`PROG_ROM_ADD7`
41			`VEC_TABLE8'hff`
42			`STARTUP"NONE"`
43			`FONT"NONE"`
44			`CLOCK_FREQ50`
45			`CLOCK_PLL_MULT2`
46			`CLOCK_PLL_DIV4`
47			`CLOCK_PLL_SIZE4`
48			`CLOCK_SRC0`
49			`RESET_SENSE0`
50			`UART_PRESCALE5'b01100`
51			`UART_PRE_SIZE5`
52			`UART_DIV0`
53			`JTAG_USER1_WIDTH8`
54			`JTAG_USER1_RESET8'h12`
55
56
57

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_dut.params.xml] - Blame information for rev 135