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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default_lint
 
 
 
 
 
 
 
 

 
       
 
              
              Dut
              
              
                                   ipxact:library="fpgas"
                                   ipxact:name="Nexys2_T6502"
                                   ipxact:version="default_dut.params"/>
              
              
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 
 
 

 
 
 
 
  
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/Nexys2_T6502_default_lint
        verilogSource
        module
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default_lint`
40	131	jt_eaton
41
42
43
44
45
46
47	133	jt_eaton
48	135	jt_eaton
49	131	jt_eaton
50	135	jt_eaton
51	131	jt_eaton
52	135	jt_eaton
53			`Dut`
54
55
56			`ipxact:library="fpgas"`
57			`ipxact:name="Nexys2_T6502"`
58			`ipxact:version="default_dut.params"/>`
59
60
61	131	jt_eaton
62	135	jt_eaton
63			`lint`
64			`:Lint:`
65			`Verilog`
66			`fs-lint`
67
68	131	jt_eaton
69	135	jt_eaton
70			`rtl_check`
71
72
73			`ipxact:library="Testbench"`
74			`ipxact:name="toolflow"`
75			`ipxact:version="rtl_check"/>`
76
77
78	131	jt_eaton
79	135	jt_eaton
80	131	jt_eaton
81
82
83
84	135	jt_eaton
85	131	jt_eaton
86
87
88
89	135	jt_eaton
90	131	jt_eaton
91
92	135	jt_eaton
93			`fs-lint`
94	131	jt_eaton
95	135	jt_eaton
96
97			`../verilog/lint/Nexys2_T6502_default_lint`
98			`verilogSource`
99			`module`
100
101	131	jt_eaton
102
103
104	135	jt_eaton
105	131	jt_eaton
106
107
108
109
110	135	jt_eaton
111	131	jt_eaton
112
113
114
115	135	jt_eaton
116	131	jt_eaton
117
118
119
120
121

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_lint.xml] - Blame information for rev 135