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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [syn/] [ise/] [Nexys2_T6502_kim_2/] [xml/] [Nexys2_T6502_kim_2.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
fpgas
Nexys2_T6502
kim_2
 
 

 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
   
      local_parameters
    
    
      destination
      top.T6502_kim_2.syn
    
  

 
 
 

 
 
 
 
  
 
 
 
    
      fs-syn
 
      
        
        ../verilog/syn/top.T6502_kim_2.syn
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 

 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
  
 
    
    Hierarchical
        Hierarchical
 
    
 
   
     Pad_Ring
 
     
     
                          ipxact:library="Nexys2"
                          ipxact:name="fpga"
                          ipxact:version="padring"/>
     
 
 
    
 
 
    
     Chip
     
     
                          ipxact:library="fpgas"
                          ipxact:name="Nexys2_T6502"
                          ipxact:version="chip"/>
     
    
 
     
     ise
     
     
                          ipxact:library="Testbench"
                          ipxact:name="toolflow"
                          ipxact:version="ise"/>
     
     
 
    
    syn:*Synthesis:*
 
    Verilog
    
    fs-syn
    
 
 
 
 

 
 

 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`kim_2`
40	131	jt_eaton
41
42	135	jt_eaton
43	131	jt_eaton
44
45
46	135	jt_eaton
47			`gen_verilog_syn`
48			`104.0`
49			`none`
50			`:Synthesis:`
51			`tools/verilog/gen_verilog`
52
53
54			`local_parameters`
55
56
57			`destination`
58			`top.T6502_kim_2.syn`
59
60
61
62	131	jt_eaton
63
64
65	135	jt_eaton
66	131	jt_eaton
67
68
69
70	135	jt_eaton
71	131	jt_eaton
72
73
74	135	jt_eaton
75			`fs-syn`
76	131	jt_eaton
77	135	jt_eaton
78
79			`../verilog/syn/top.T6502_kim_2.syn`
80			`verilogSourcemodule`
81
82	131	jt_eaton
83	135	jt_eaton
84	131	jt_eaton
85
86
87
88	135	jt_eaton
89	131	jt_eaton
90
91
92
93	135	jt_eaton
94	131	jt_eaton
95
96	135	jt_eaton
97
98			`Hierarchical`
99
100
101
102	131	jt_eaton
103	135	jt_eaton
104	131	jt_eaton
105	135	jt_eaton
106
107
108			`Hierarchical`
109			`Hierarchical`
110
111
112
113
114			`Pad_Ring`
115	131	jt_eaton
116	135	jt_eaton
117
118			`ipxact:library="Nexys2"`
119			`ipxact:name="fpga"`
120			`ipxact:version="padring"/>`
121
122	131	jt_eaton
123
124	135	jt_eaton
125	131	jt_eaton
126
127	135	jt_eaton
128			`Chip`
129
130
131			`ipxact:library="fpgas"`
132			`ipxact:name="Nexys2_T6502"`
133			`ipxact:version="chip"/>`
134
135
136	131	jt_eaton
137	135	jt_eaton
138			`ise`
139
140
141			`ipxact:library="Testbench"`
142			`ipxact:name="toolflow"`
143			`ipxact:version="ise"/>`
144
145
146	131	jt_eaton
147	135	jt_eaton
148			`syn:Synthesis:`
149	131	jt_eaton
150	135	jt_eaton	`Verilog`
151
152			`fs-syn`
153
154	131	jt_eaton
155
156	135	jt_eaton
157	131	jt_eaton
158	135	jt_eaton
159	131	jt_eaton
160
161	135	jt_eaton
162	131	jt_eaton
163
164
165
166
167
168
169
170
171
172

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [syn/] [ise/] [Nexys2_T6502_kim_2/] [xml/] [Nexys2_T6502_kim_2.xml] - Blame information for rev 135