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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [doc/] [sch/] [io_module_gpio.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
C 1900 300 1 0 0 in_port_vector.sym
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{
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T 1900 300 5 10 1 1 0 6 1 1
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refdes=reg_mb_wdata[7:0]
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}
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C 1900 700 1 0 0 in_port_vector.sym
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{
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T 1900 700 5 10 1 1 0 6 1 1
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refdes=reg_mb_addr[7:0]
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}
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C 1900 1100 1 0 0 in_port_vector.sym
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{
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T 1900 1100 5 10 1 1 0 6 1 1
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refdes=pic_irq_in[7:0]
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}
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C 1900 1500 1 0 0 in_port_vector.sym
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{
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T 1900 1500 5 10 1 1 0 6 1 1
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refdes=gpio_1_in[7:0]
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}
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C 1900 1900 1 0 0 in_port_vector.sym
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{
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T 1900 1900 5 10 1 1 0 6 1 1
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refdes=gpio_0_in[7:0]
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}
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C 1900 2300 1 0 0 in_port.sym
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{
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T 1900 2300 5 10 1 1 0 6 1 1
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refdes=uart_rxd_pad_in
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}
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C 1900 2700 1 0 0 in_port.sym
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{
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T 1900 2700 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1900 3100 1 0 0 in_port.sym
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{
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T 1900 3100 5 10 1 1 0 6 1 1
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refdes=reg_mb_wr
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}
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C 1900 3500 1 0 0 in_port.sym
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{
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T 1900 3500 5 10 1 1 0 6 1 1
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refdes=reg_mb_rd
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}
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C 1900 3900 1 0 0 in_port.sym
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{
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T 1900 3900 5 10 1 1 0 6 1 1
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refdes=reg_mb_cs
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}
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C 1900 4300 1 0 0 in_port.sym
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{
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T 1900 4300 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 1900 4700 1 0 0 in_port.sym
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{
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T 1900 4700 5 10 1 1 0 6 1 1
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refdes=cts_pad_in
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}
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C 1900 5100 1 0 0 in_port.sym
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{
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T 1900 5100 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 5000 300  1 0  0 out_port_vector.sym
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{
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T 6000 300 5  10 1 1 0 0 1 1
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refdes=timer_irq[1:0]
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}
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C 5000 700  1 0  0 out_port_vector.sym
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{
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T 6000 700 5  10 1 1 0 0 1 1
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refdes=reg_mb_rdata[15:0]
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}
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C 5000 1100  1 0  0 out_port_vector.sym
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{
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T 6000 1100 5  10 1 1 0 0 1 1
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refdes=gpio_1_out[7:0]
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}
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C 5000 1500  1 0  0 out_port_vector.sym
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{
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T 6000 1500 5  10 1 1 0 0 1 1
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refdes=gpio_1_oe[7:0]
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}
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C 5000 1900  1 0  0 out_port_vector.sym
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{
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T 6000 1900 5  10 1 1 0 0 1 1
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refdes=gpio_0_out[7:0]
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}
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C 5000 2300  1 0  0 out_port_vector.sym
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{
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T 6000 2300 5  10 1 1 0 0 1 1
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refdes=gpio_0_oe[7:0]
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}
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C 5000 2700  1 0 0 out_port.sym
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{
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T 6000 2700 5  10 1 1 0 0 1 1
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refdes=wait_n
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}
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C 5000 3100  1 0 0 out_port.sym
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{
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T 6000 3100 5  10 1 1 0 0 1 1
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refdes=uart_txd_pad_out
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}
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C 5000 3500  1 0 0 out_port.sym
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{
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T 6000 3500 5  10 1 1 0 0 1 1
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refdes=tx_irq
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}
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C 5000 3900  1 0 0 out_port.sym
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{
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T 6000 3900 5  10 1 1 0 0 1 1
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refdes=rx_irq
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}
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C 5000 4300  1 0 0 out_port.sym
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{
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T 6000 4300 5  10 1 1 0 0 1 1
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refdes=rts_pad_out
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}
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C 5000 4700  1 0 0 out_port.sym
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{
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T 6000 4700 5  10 1 1 0 0 1 1
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refdes=reg_mb_wait
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}
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C 5000 5100  1 0 0 out_port.sym
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{
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T 6000 5100 5  10 1 1 0 0 1 1
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refdes=pic_nmi
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}
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C 5000 5500  1 0 0 out_port.sym
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{
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T 6000 5500 5  10 1 1 0 0 1 1
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refdes=pic_irq
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}

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