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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [doc/] [sch/] [io_uart_tx.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton
v 20100214 1
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C 1700 300 1 0 0 in_port_vector.sym
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{
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T 1700 300 5 10 1 1 0 6 1 1
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refdes=wdata[7:0]
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}
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C 1700 700 1 0 0 in_port_vector.sym
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{
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T 1700 700 5 10 1 1 0 6 1 1
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refdes=addr[3:0]
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}
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C 1700 1100 1 0 0 in_port.sym
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{
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T 1700 1100 5 10 1 1 0 6 1 1
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refdes=wr
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}
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C 1700 1500 1 0 0 in_port.sym
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{
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T 1700 1500 5 10 1 1 0 6 1 1
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refdes=uart_rxd_pad_in
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}
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C 1700 1900 1 0 0 in_port.sym
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{
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T 1700 1900 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1700 2300 1 0 0 in_port.sym
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{
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T 1700 2300 5 10 1 1 0 6 1 1
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refdes=rd
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}
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C 1700 2700 1 0 0 in_port.sym
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{
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T 1700 2700 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 1700 3100 1 0 0 in_port.sym
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{
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T 1700 3100 5 10 1 1 0 6 1 1
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refdes=cts_pad_in
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}
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C 1700 3500 1 0 0 in_port.sym
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{
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T 1700 3500 5 10 1 1 0 6 1 1
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refdes=cs
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}
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C 1700 3900 1 0 0 in_port.sym
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{
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T 1700 3900 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 4600 300  1 0  0 out_port_vector.sym
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{
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T 5600 300 5  10 1 1 0 0 1 1
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refdes=rdata[7:0]
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}
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C 4600 700  1 0 0 out_port.sym
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{
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T 5600 700 5  10 1 1 0 0 1 1
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refdes=uart_txd_pad_out
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}
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C 4600 1100  1 0 0 out_port.sym
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{
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T 5600 1100 5  10 1 1 0 0 1 1
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refdes=tx_irq
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}
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C 4600 1500  1 0 0 out_port.sym
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{
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T 5600 1500 5  10 1 1 0 0 1 1
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refdes=rx_irq
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}
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C 4600 1900  1 0 0 out_port.sym
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{
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T 5600 1900 5  10 1 1 0 0 1 1
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refdes=rts_pad_out
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}

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