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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [doc/] [sym/] [io_module_mouse.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  3900 4900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 5050   5 10 1 1 0 0 1 1
4 
device=io_module_mouse
5 
T 400 5250 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 5400    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 5400    0 10 0 1 0 0 1 1
10 
library=io
11 
T 400 5400    0 10 0 1 0 0 1 1
12 
component=io_module
13 
T 400 5400    0 10 0 1 0 0 1 1
14 
version=mouse
15 
P 300 200 0 200 10 1 1
16 
{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=reg_mb_wdata[7:0]
19 
T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 10 1 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=reg_mb_addr[7:0]
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 10 1 1
30 
{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=pic_irq_in[7:0]
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 10 1 1
37 
{
38 
T 400 800 5 10 1 1 0 1 1 1
39 
pinnumber=gpio_1_in[7:0]
40 
T 400 800 5 10 0 1 0 1 1 1
41 
pinseq=4
42 
}
43 
P 300 1000 0 1000 10 1 1
44 
{
45 
T 400 1000 5 10 1 1 0 1 1 1
46 
pinnumber=gpio_0_in[7:0]
47 
T 400 1000 5 10 0 1 0 1 1 1
48 
pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
51 
{
52 
T 400 1200 5 10 1 1 0 1 1 1
53 
pinnumber=uart_rxd_pad_in
54 
T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=reset
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 300 1600 0 1600 4 0 1
65 
{
66 
T 400 1600 5 10 1 1 0 1 1 1
67 
pinnumber=reg_mb_wr
68 
T 400 1600 5 10 0 1 0 1 1 1
69 
pinseq=8
70 
}
71 
P 300 1800 0 1800 4 0 1
72 
{
73 
T 400 1800 5 10 1 1 0 1 1 1
74 
pinnumber=reg_mb_rd
75 
T 400 1800 5 10 0 1 0 1 1 1
76 
pinseq=9
77 
}
78 
P 300 2000 0 2000 4 0 1
79 
{
80 
T 400 2000 5 10 1 1 0 1 1 1
81 
pinnumber=reg_mb_cs
82 
T 400 2000 5 10 0 1 0 1 1 1
83 
pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
86 
{
87 
T 400 2200 5 10 1 1 0 1 1 1
88 
pinnumber=ps2_data_pad_in
89 
T 400 2200 5 10 0 1 0 1 1 1
90 
pinseq=11
91 
}
92 
P 300 2400 0 2400 4 0 1
93 
{
94 
T 400 2400 5 10 1 1 0 1 1 1
95 
pinnumber=ps2_clk_pad_in
96 
T 400 2400 5 10 0 1 0 1 1 1
97 
pinseq=12
98 
}
99 
P 300 2600 0 2600 4 0 1
100 
{
101 
T 400 2600 5 10 1 1 0 1 1 1
102 
pinnumber=enable
103 
T 400 2600 5 10 0 1 0 1 1 1
104 
pinseq=13
105 
}
106 
P 300 2800 0 2800 4 0 1
107 
{
108 
T 400 2800 5 10 1 1 0 1 1 1
109 
pinnumber=cts_pad_in
110 
T 400 2800 5 10 0 1 0 1 1 1
111 
pinseq=14
112 
}
113 
P 300 3000 0 3000 4 0 1
114 
{
115 
T 400 3000 5 10 1 1 0 1 1 1
116 
pinnumber=clk
117 
T 400 3000 5 10 0 1 0 1 1 1
118 
pinseq=15
119 
}
120 
P 4200 200 4500 200 10 1 1
121 
{
122 
T 4100 200 5  10 1 1 0 7 1 1
123 
pinnumber=y_pos[9:0]
124 
T 4100 200 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}
127 
P 4200 400 4500 400 10 1 1
128 
{
129 
T 4100 400 5  10 1 1 0 7 1 1
130 
pinnumber=x_pos[9:0]
131 
T 4100 400 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 4200 600 4500 600 10 1 1
135 
{
136 
T 4100 600 5  10 1 1 0 7 1 1
137 
pinnumber=timer_irq[1:0]
138 
T 4100 600 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}
141 
P 4200 800 4500 800 10 1 1
142 
{
143 
T 4100 800 5  10 1 1 0 7 1 1
144 
pinnumber=reg_mb_rdata[15:0]
145 
T 4100 800 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}
148 
P 4200 1000 4500 1000 10 1 1
149 
{
150 
T 4100 1000 5  10 1 1 0 7 1 1
151 
pinnumber=gpio_1_out[7:0]
152 
T 4100 1000 5  10 0 1 0 7 1 1
153 
pinseq=20
154 
}
155 
P 4200 1200 4500 1200 10 1 1
156 
{
157 
T 4100 1200 5  10 1 1 0 7 1 1
158 
pinnumber=gpio_1_oe[7:0]
159 
T 4100 1200 5  10 0 1 0 7 1 1
160 
pinseq=21
161 
}
162 
P 4200 1400 4500 1400 10 1 1
163 
{
164 
T 4100 1400 5  10 1 1 0 7 1 1
165 
pinnumber=gpio_0_out[7:0]
166 
T 4100 1400 5  10 0 1 0 7 1 1
167 
pinseq=22
168 
}
169 
P 4200 1600 4500 1600 10 1 1
170 
{
171 
T 4100 1600 5  10 1 1 0 7 1 1
172 
pinnumber=gpio_0_oe[7:0]
173 
T 4100 1600 5  10 0 1 0 7 1 1
174 
pinseq=23
175 
}
176 
P 4200 1800 4500 1800 4 0 1
177 
{
178 
T 4100 1800 5  10 1 1 0 7 1 1
179 
pinnumber=wait_n
180 
T 4200 1800 5  10 0 1 0 7 1 1
181 
pinseq=24
182 
}
183 
P 4200 2000 4500 2000 4 0 1
184 
{
185 
T 4100 2000 5  10 1 1 0 7 1 1
186 
pinnumber=uart_txd_pad_out
187 
T 4200 2000 5  10 0 1 0 7 1 1
188 
pinseq=25
189 
}
190 
P 4200 2200 4500 2200 4 0 1
191 
{
192 
T 4100 2200 5  10 1 1 0 7 1 1
193 
pinnumber=tx_irq
194 
T 4200 2200 5  10 0 1 0 7 1 1
195 
pinseq=26
196 
}
197 
P 4200 2400 4500 2400 4 0 1
198 
{
199 
T 4100 2400 5  10 1 1 0 7 1 1
200 
pinnumber=rx_irq
201 
T 4200 2400 5  10 0 1 0 7 1 1
202 
pinseq=27
203 
}
204 
P 4200 2600 4500 2600 4 0 1
205 
{
206 
T 4100 2600 5  10 1 1 0 7 1 1
207 
pinnumber=rts_pad_out
208 
T 4200 2600 5  10 0 1 0 7 1 1
209 
pinseq=28
210 
}
211 
P 4200 2800 4500 2800 4 0 1
212 
{
213 
T 4100 2800 5  10 1 1 0 7 1 1
214 
pinnumber=reg_mb_wait
215 
T 4200 2800 5  10 0 1 0 7 1 1
216 
pinseq=29
217 
}
218 
P 4200 3000 4500 3000 4 0 1
219 
{
220 
T 4100 3000 5  10 1 1 0 7 1 1
221 
pinnumber=ps2_data_pad_oe
222 
T 4200 3000 5  10 0 1 0 7 1 1
223 
pinseq=30
224 
}
225 
P 4200 3200 4500 3200 4 0 1
226 
{
227 
T 4100 3200 5  10 1 1 0 7 1 1
228 
pinnumber=ps2_data_avail
229 
T 4200 3200 5  10 0 1 0 7 1 1
230 
pinseq=31
231 
}
232 
P 4200 3400 4500 3400 4 0 1
233 
{
234 
T 4100 3400 5  10 1 1 0 7 1 1
235 
pinnumber=ps2_clk_pad_oe
236 
T 4200 3400 5  10 0 1 0 7 1 1
237 
pinseq=32
238 
}
239 
P 4200 3600 4500 3600 4 0 1
240 
{
241 
T 4100 3600 5  10 1 1 0 7 1 1
242 
pinnumber=pic_nmi
243 
T 4200 3600 5  10 0 1 0 7 1 1
244 
pinseq=33
245 
}
246 
P 4200 3800 4500 3800 4 0 1
247 
{
248 
T 4100 3800 5  10 1 1 0 7 1 1
249 
pinnumber=pic_irq
250 
T 4200 3800 5  10 0 1 0 7 1 1
251 
pinseq=34
252 
}
253 
P 4200 4000 4500 4000 4 0 1
254 
{
255 
T 4100 4000 5  10 1 1 0 7 1 1
256 
pinnumber=new_packet
257 
T 4200 4000 5  10 0 1 0 7 1 1
258 
pinseq=35
259 
}
260 
P 4200 4200 4500 4200 4 0 1
261 
{
262 
T 4100 4200 5  10 1 1 0 7 1 1
263 
pinnumber=ms_right
264 
T 4200 4200 5  10 0 1 0 7 1 1
265 
pinseq=36
266 
}
267 
P 4200 4400 4500 4400 4 0 1
268 
{
269 
T 4100 4400 5  10 1 1 0 7 1 1
270 
pinnumber=ms_mid
271 
T 4200 4400 5  10 0 1 0 7 1 1
272 
pinseq=37
273 
}
274 
P 4200 4600 4500 4600 4 0 1
275 
{
276 
T 4100 4600 5  10 1 1 0 7 1 1
277 
pinnumber=ms_left
278 
T 4200 4600 5  10 0 1 0 7 1 1
279 
pinseq=38
280 
}

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