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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_module
gpio
 

 
 slave_clk
  
  
      
      
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 

 

 
 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_module_gpio
    
  

 
 
 

 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.gpio.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_gpio
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
   
 
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_gpio
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 

 
 
 
 
 

        
                        
                                Hierarchical
                                
                        
                
 
       
 
              
              Hierarchical
               Hierarchical
 
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

 
 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 

 
 

 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 

 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_module`
40			`gpio`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton	`slave_clk`
45
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58
59	131	jt_eaton
60
61	135	jt_eaton	`slave_reset`
62
63
64
65
66
67
68			`reset`
69			`reset`
70
71
72
73
74
75
76	131	jt_eaton
77	135	jt_eaton
78	131	jt_eaton
79	135	jt_eaton
80	131	jt_eaton
81
82
83
84
85
86	133	jt_eaton
87	135	jt_eaton
88			`gen_registers`
89			`102.1`
90			`:common:`
91			`none`
92			`tools/regtool/gen_registers`
93
94
95			`bus_intf`
96			`mb`
97
98
99			`dest_dir`
100			`../verilog`
101
102
103
104	131	jt_eaton
105
106
107	135	jt_eaton
108			`gen_verilog`
109			`104.0`
110			`none`
111			`:common:`
112			`tools/verilog/gen_verilog`
113
114
115			`destination`
116			`io_module_gpio`
117
118
119
120	131	jt_eaton
121
122
123	135	jt_eaton
124	131	jt_eaton
125
126	135	jt_eaton
127	131	jt_eaton
128	135	jt_eaton
129			`fs-common`
130	131	jt_eaton
131
132	135	jt_eaton
133
134			`../verilog/top.gpio.rtl`
135			`verilogSourcefragment`
136
137	131	jt_eaton
138	135	jt_eaton
139	131	jt_eaton
140
141	135	jt_eaton
142			`fs-sim`
143	131	jt_eaton
144	135	jt_eaton
145
146			`../verilog/copyright`
147			`verilogSourceinclude`
148
149	131	jt_eaton
150	135	jt_eaton
151
152			`../verilog/common/io_module_gpio`
153			`verilogSourcemodule`
154
155	131	jt_eaton
156
157	135	jt_eaton
158			`dest_dir`
159			`../views/sim/`
160			`verilogSourcelibraryDir`
161
162	134	jt_eaton
163
164	135	jt_eaton
165	131	jt_eaton
166
167	135	jt_eaton
168			`fs-syn`
169	131	jt_eaton
170
171	135	jt_eaton
172
173			`../verilog/copyright`
174			`verilogSourceinclude`
175
176	131	jt_eaton
177	135	jt_eaton
178
179			`../verilog/common/io_module_gpio`
180			`verilogSourcemodule`
181
182	131	jt_eaton
183
184	135	jt_eaton
185			`dest_dir`
186			`../views/syn/`
187			`verilogSourcelibraryDir`
188
189	131	jt_eaton
190	134	jt_eaton
191
192	135	jt_eaton
193	131	jt_eaton
194
195
196
197
198	135	jt_eaton
199	131	jt_eaton
200
201
202
203
204	135	jt_eaton
205
206
207			`Hierarchical`
208
209
210
211
212
213	131	jt_eaton
214	135	jt_eaton
215			`Hierarchical`
216			`Hierarchical`
217	131	jt_eaton
218	135	jt_eaton
219	131	jt_eaton
220	135	jt_eaton
221			`verilog`
222
223
224			`ipxact:library="Testbench"`
225			`ipxact:name="toolflow"`
226			`ipxact:version="verilog"/>`
227
228
229	131	jt_eaton
230
231
232
233
234	135	jt_eaton
235			`common:common:`
236			`Verilog`
237
238
239			`fs-common`
240
241
242	131	jt_eaton
243	135	jt_eaton
244			`sim:Simulation:`
245			`Verilog`
246
247
248			`fs-sim`
249
250
251	131	jt_eaton
252
253	135	jt_eaton
254			`syn:Synthesis:`
255			`Verilog`
256
257
258			`fs-syn`
259
260
261	131	jt_eaton
262
263
264	135	jt_eaton
265			`doc`
266
267
268			`ipxact:library="Testbench"`
269			`ipxact:name="toolflow"`
270			`ipxact:version="documentation"/>`
271
272			`:Documentation:`
273			`Verilog`
274
275	131	jt_eaton
276
277
278	135	jt_eaton
279	131	jt_eaton
280
281
282
283
284
285
286	135	jt_eaton
287	131	jt_eaton
288
289
290	135	jt_eaton
291			`clk`
292			`wire`
293			`in`
294
295	131	jt_eaton
296
297	135	jt_eaton	`reset`
298			`wire`
299			`in`
300
301	131	jt_eaton
302
303
304	135	jt_eaton	`enable`
305			`wire`
306			`in`
307
308	131	jt_eaton
309
310
311
312	135	jt_eaton	`wait_n`
313			`wire`
314			`out`
315
316	131	jt_eaton
317
318	135	jt_eaton	`gpio_0_out`
319			`wire`
320			`out`
321			`70`
322
323	131	jt_eaton
324	135	jt_eaton	`gpio_0_oe`
325			`wire`
326			`out`
327			`70`
328
329	131	jt_eaton
330
331	135	jt_eaton	`gpio_0_in`
332			`wire`
333			`in`
334			`70`
335
336	131	jt_eaton
337	135	jt_eaton	`gpio_1_out`
338			`wire`
339			`out`
340			`70`
341
342	131	jt_eaton
343	135	jt_eaton	`gpio_1_oe`
344			`wire`
345			`out`
346			`70`
347
348	131	jt_eaton
349
350
351	135	jt_eaton	`gpio_1_in`
352			`wire`
353			`in`
354			`70`
355
356	131	jt_eaton
357	135	jt_eaton	`timer_irq`
358			`wire`
359			`out`
360			`10`
361
362	131	jt_eaton
363	135	jt_eaton	`pic_irq`
364			`wire`
365			`out`
366
367	131	jt_eaton
368	135	jt_eaton	`pic_nmi`
369			`wire`
370			`out`
371
372	131	jt_eaton
373	135	jt_eaton	`pic_irq_in`
374			`wire`
375			`in`
376			`70`
377
378	131	jt_eaton
379
380	135	jt_eaton	`cts_pad_in`
381			`wire`
382			`in`
383
384	131	jt_eaton
385	135	jt_eaton	`rts_pad_out`
386			`wire`
387			`out`
388
389	131	jt_eaton
390	135	jt_eaton	`rx_irq`
391			`wire`
392			`out`
393
394	131	jt_eaton
395	135	jt_eaton	`tx_irq`
396			`wire`
397			`out`
398
399
400
401
402
403
404
405
406
407
408
409			`8`
410			`mb`
411
412			`mb`
413			`0x00`
414	131	jt_eaton
415	135	jt_eaton
416			`gpio`
417			`0x10`
418			`8`
419	131	jt_eaton
420
421	135	jt_eaton
422			`0_out`
423			`0x2`
424			`8`
425			`read-write`
426
427	131	jt_eaton
428	135	jt_eaton
429			`0_oe`
430			`0x1`
431			`8`
432			`read-write`
433
434	131	jt_eaton
435	135	jt_eaton
436			`0_in`
437			`0x0`
438			`8`
439			`read-only`
440
441	131	jt_eaton
442
443	135	jt_eaton
444			`1_out`
445			`0x6`
446			`8`
447			`read-write`
448
449	131	jt_eaton
450	135	jt_eaton
451			`1_oe`
452			`0x5`
453			`8`
454			`read-write`
455
456	131	jt_eaton
457	135	jt_eaton
458			`1_in`
459			`0x4`
460			`8`
461			`read-only`
462
463	131	jt_eaton
464
465	135	jt_eaton
466	131	jt_eaton
467
468	135	jt_eaton
469	131	jt_eaton
470	135	jt_eaton
471	131	jt_eaton
472
473
474
475
476	135	jt_eaton
477	131	jt_eaton
478
479
480
481