URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [componentCfg.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
io
io_pic
 
2
_
_
_
VARIANT

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 

 

default
def
def_lint

 IRQ_MODE8'h00
 NMI_MODE8'h00



 
 
 
 

 
io_pic/sim
 
 
 
 

 
 
 

io_pic_def_lint
def_lint

  rtl_check



 
 
 
 


default
io_pic_def_lint


 
 
 
 
 

 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`io`
12			`io_pic`
13
14			`2`
15			`_`
16			`_`
17			`_`
18			`VARIANT`
19	135	jt_eaton
20
21			`TestBenches`
22			`sim`
23			`testbenches`
24			`testbench`
25			`version`
26
27
28			`Fpgas`
29			`syn`
30			`ise`
31			`chip`
32			`variant`
33
34
35	131	jt_eaton
36	135	jt_eaton
37
38	131	jt_eaton
39
40			`/doc`
41
42
43
44	134	jt_eaton
45
46
47			`default`
48			`def`
49			`def_lint`
50
51			`IRQ_MODE8'h00`
52			`NMI_MODE8'h00`
53
54
55
56
57
58
59
60	131	jt_eaton
61
62			`io_pic/sim`
63
64
65
66
67
68
69
70
71
72			`io_pic_def_lint`
73			`def_lint`
74
75			`rtl_check`
76
77
78
79
80
81
82
83
84
85			`default`
86			`io_pic_def_lint`
87
88
89
90
91
92
93
94
95
96
97

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [componentCfg.xml] - Blame information for rev 135