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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_rxtx.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_uart
rxtx
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
mb
   
  
      
   
   
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
        
      
 
   little
   8
     
 
 
  
 
 
 

 
 
 

 
 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      io_uart_rxtx
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_uart_rxtx
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_rxtx_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
  
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
       
 
              
              Hierarchical
               Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 

 
 
enable
wire
in

 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_rxtx.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_uart`
40			`rxtx`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81	135	jt_eaton	`mb`
82
83
84
85
86
87
88			`rdata`
89
90			`rdata`
91			`wire`
92			`70`
93
94
95	131	jt_eaton
96	135	jt_eaton
97			`addr`
98
99			`addr`
100			`30`
101
102
103	131	jt_eaton
104	135	jt_eaton
105			`wdata`
106
107			`wdata`
108			`70`
109
110
111	131	jt_eaton
112
113	135	jt_eaton
114			`rd`
115
116			`rd`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`wr`
122
123			`wr`
124
125
126	131	jt_eaton
127	135	jt_eaton
128			`cs`
129
130			`cs`
131
132
133	131	jt_eaton
134	135	jt_eaton
135
136
137	131	jt_eaton
138	135	jt_eaton	`little`
139			`8`
140
141	131	jt_eaton
142
143	135	jt_eaton
144	131	jt_eaton
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151	135	jt_eaton
152	131	jt_eaton
153
154
155	133	jt_eaton
156	131	jt_eaton
157
158
159	135	jt_eaton
160			`gen_registers`
161			`102.1`
162			`:common:`
163			`none`
164			`tools/regtool/gen_registers`
165
166
167			`bus_intf`
168			`mb`
169
170
171			`dest_dir`
172			`../verilog`
173
174
175
176	131	jt_eaton
177	135	jt_eaton
178			`gen_verilog`
179			`104.0`
180			`none`
181			`:common:`
182			`tools/verilog/gen_verilog`
183
184
185			`destination`
186			`io_uart_rxtx`
187
188
189
190	131	jt_eaton
191
192
193
194	135	jt_eaton
195	131	jt_eaton
196
197
198	135	jt_eaton
199	131	jt_eaton
200	135	jt_eaton
201			`fs-common`
202	131	jt_eaton
203	135	jt_eaton
204
205			`../verilog/top.body`
206			`verilogSourcefragment`
207
208	131	jt_eaton
209	135	jt_eaton
210	131	jt_eaton
211	135	jt_eaton
212			`fs-sim`
213	131	jt_eaton
214	135	jt_eaton
215
216			`../verilog/copyright.v`
217			`verilogSourceinclude`
218
219	131	jt_eaton
220	135	jt_eaton
221
222			`../verilog/common/io_uart_rxtx`
223			`verilogSourcemodule`
224
225	131	jt_eaton
226	135	jt_eaton
227			`mb`
228			`../verilog/io_uart_rxtx_mb`
229			`verilogSourcemodule`
230
231	131	jt_eaton
232
233
234	135	jt_eaton
235	131	jt_eaton
236
237
238	135	jt_eaton
239	131	jt_eaton
240
241
242
243	135	jt_eaton
244	131	jt_eaton
245	135	jt_eaton
246
247			`Hierarchical`
248
249
250
251	131	jt_eaton
252
253	135	jt_eaton
254
255	131	jt_eaton
256	135	jt_eaton
257			`Hierarchical`
258			`Hierarchical`
259	131	jt_eaton
260	135	jt_eaton
261	131	jt_eaton
262
263	135	jt_eaton
264			`verilog`
265
266
267			`ipxact:library="Testbench"`
268			`ipxact:name="toolflow"`
269			`ipxact:version="verilog"/>`
270
271
272	131	jt_eaton
273
274
275
276
277	135	jt_eaton
278			`common:common:`
279			`Verilog`
280
281
282			`fs-common`
283
284
285	131	jt_eaton
286	135	jt_eaton
287			`sim:Simulation:`
288			`Verilog`
289
290
291			`fs-sim`
292
293
294	131	jt_eaton
295
296	135	jt_eaton
297			`syn:Synthesis:`
298			`Verilog`
299
300
301			`fs-sim`
302
303
304	131	jt_eaton
305
306	135	jt_eaton
307			`doc`
308
309
310			`ipxact:library="Testbench"`
311			`ipxact:name="toolflow"`
312			`ipxact:version="documentation"/>`
313
314			`:Documentation:`
315			`Verilog`
316
317	131	jt_eaton
318
319
320	135	jt_eaton
321	131	jt_eaton
322
323
324
325
326
327	135	jt_eaton
328	131	jt_eaton
329
330	135	jt_eaton	`enable`
331			`wire`
332			`in`
333
334	131	jt_eaton
335	135	jt_eaton
336			`clk`
337			`wire`
338			`in`
339
340	131	jt_eaton
341
342	135	jt_eaton	`reset`
343			`wire`
344			`in`
345
346	131	jt_eaton
347
348	135	jt_eaton	`cs`
349			`wire`
350			`in`
351
352	131	jt_eaton
353
354	135	jt_eaton	`rd`
355			`wire`
356			`in`
357
358	131	jt_eaton
359	135	jt_eaton	`wr`
360			`wire`
361			`in`
362
363
364
365			`addr`
366			`wire`
367			`in`
368			`30`
369
370
371
372			`wdata`
373			`wire`
374			`in`
375			`70`
376
377
378
379			`rdata`
380			`wire`
381			`out`
382			`70`
383
384
385
386
387
388
389			`cts_pad_in`
390			`wire`
391			`in`
392
393
394			`rts_pad_out`
395			`wire`
396			`out`
397
398
399			`rx_irq`
400			`reg`
401			`out`
402
403
404			`tx_irq`
405			`reg`
406			`out`
407
408
409
410
411
412
413
414
415
416
417
418
419
420			`mb`
421			`8`
422
423			`mb`
424			`0x00`
425	131	jt_eaton
426	135	jt_eaton
427			`mb_microbus`
428			`0x10`
429			`8`
430	131	jt_eaton
431
432	135	jt_eaton
433			`xmit_data`
434			`0x0`
435			`8`
436			`write-only`
437
438	131	jt_eaton
439	135	jt_eaton
440			`rcv_data`
441			`0x2`
442			`8`
443			`read-only`
444
445	131	jt_eaton
446
447	135	jt_eaton
448			`cntrl`
449			`0x4`
450			`8`
451			`read-write`
452
453	131	jt_eaton
454	135	jt_eaton
455			`status`
456			`0x6`
457			`8`
458			`read-only`
459
460	131	jt_eaton
461
462	135	jt_eaton
463	131	jt_eaton
464
465	135	jt_eaton
466	131	jt_eaton
467	135	jt_eaton
468	131	jt_eaton
469
470
471
472	135	jt_eaton