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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_tx.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_uart
tx
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
        
      
   little
   8
     
  
 
 
 

 
 
 

 
 
 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_uart_tx
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_uart_tx
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_tx_mb
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
  
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
       
 
              
              Hierarchical
               Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

 
 
enable
wire
in

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_tx.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_uart`
40			`tx`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81	135	jt_eaton	`mb`
82
83
84
85
86
87
88			`rdata`
89
90			`rdata`
91			`wire`
92			`70`
93
94
95	131	jt_eaton
96	135	jt_eaton
97			`addr`
98
99			`addr`
100			`30`
101
102
103	131	jt_eaton
104	135	jt_eaton
105			`wdata`
106
107			`wdata`
108			`70`
109
110
111	131	jt_eaton
112
113	135	jt_eaton
114			`rd`
115
116			`rd`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`wr`
122
123			`wr`
124
125
126	131	jt_eaton
127	135	jt_eaton
128			`cs`
129
130			`cs`
131
132
133	131	jt_eaton
134	135	jt_eaton
135
136
137			`little`
138			`8`
139
140
141	131	jt_eaton
142
143
144	135	jt_eaton
145	131	jt_eaton
146
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152
153
154
155	133	jt_eaton
156
157	135	jt_eaton
158			`gen_registers`
159			`102.1`
160			`:common:`
161			`none`
162			`tools/regtool/gen_registers`
163
164
165			`bus_intf`
166			`mb`
167
168
169			`dest_dir`
170			`../verilog`
171
172
173
174	131	jt_eaton
175	135	jt_eaton
176			`gen_verilog`
177			`104.0`
178			`none`
179			`:common:`
180			`tools/verilog/gen_verilog`
181
182
183			`destination`
184			`io_uart_tx`
185
186
187
188	131	jt_eaton
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195
196	135	jt_eaton
197	131	jt_eaton
198	135	jt_eaton
199			`fs-common`
200	131	jt_eaton
201	135	jt_eaton
202
203			`../verilog/top.body`
204			`verilogSourcefragment`
205
206	131	jt_eaton
207
208	135	jt_eaton
209	131	jt_eaton
210	135	jt_eaton
211			`fs-sim`
212	131	jt_eaton
213	135	jt_eaton
214
215			`../verilog/copyright.v`
216			`verilogSourceinclude`
217
218	131	jt_eaton
219	135	jt_eaton
220
221			`../verilog/common/io_uart_tx`
222			`verilogSourcemodule`
223
224	131	jt_eaton
225	135	jt_eaton
226			`mb`
227			`../verilog/io_uart_tx_mb`
228			`verilogSourcemodule`
229
230	131	jt_eaton
231	135	jt_eaton
232	131	jt_eaton
233
234
235
236	135	jt_eaton
237	131	jt_eaton
238
239
240
241	135	jt_eaton
242	131	jt_eaton
243
244	135	jt_eaton
245
246			`Hierarchical`
247
248
249
250	131	jt_eaton
251	135	jt_eaton
252
253	131	jt_eaton
254	135	jt_eaton
255			`Hierarchical`
256			`Hierarchical`
257
258	131	jt_eaton
259
260	135	jt_eaton
261			`verilog`
262
263
264			`ipxact:library="Testbench"`
265			`ipxact:name="toolflow"`
266			`ipxact:version="verilog"/>`
267
268
269	131	jt_eaton
270
271
272
273
274	135	jt_eaton
275			`common:common:`
276			`Verilog`
277
278
279			`fs-common`
280
281
282	131	jt_eaton
283	135	jt_eaton
284			`sim:Simulation:`
285			`Verilog`
286
287
288			`fs-sim`
289
290
291	131	jt_eaton
292
293	135	jt_eaton
294			`syn:Synthesis:`
295			`Verilog`
296
297
298			`fs-sim`
299
300
301	131	jt_eaton
302
303
304	135	jt_eaton
305			`doc`
306
307
308			`ipxact:library="Testbench"`
309			`ipxact:name="toolflow"`
310			`ipxact:version="documentation"/>`
311
312			`:Documentation:`
313			`Verilog`
314
315	131	jt_eaton
316
317
318	135	jt_eaton
319	131	jt_eaton
320
321	135	jt_eaton
322	131	jt_eaton
323
324	135	jt_eaton	`enable`
325			`wire`
326			`in`
327
328	131	jt_eaton
329
330	135	jt_eaton
331			`clk`
332			`wire`
333			`in`
334
335	131	jt_eaton
336
337	135	jt_eaton	`reset`
338			`wire`
339			`in`
340
341	131	jt_eaton
342
343	135	jt_eaton	`cs`
344			`wire`
345			`in`
346
347	131	jt_eaton
348
349	135	jt_eaton	`rd`
350			`wire`
351			`in`
352
353	131	jt_eaton
354	135	jt_eaton	`wr`
355			`wire`
356			`in`
357
358	131	jt_eaton
359
360	135	jt_eaton	`addr`
361			`wire`
362			`in`
363			`30`
364
365	131	jt_eaton
366
367	135	jt_eaton	`wdata`
368			`wire`
369			`in`
370			`70`
371
372	131	jt_eaton
373
374	135	jt_eaton	`rdata`
375			`wire`
376			`out`
377			`70`
378
379
380
381
382
383
384			`cts_pad_in`
385			`wire`
386			`in`
387
388
389			`rts_pad_out`
390			`wire`
391			`out`
392
393
394			`rx_irq`
395			`reg`
396			`out`
397
398
399			`tx_irq`
400			`reg`
401			`out`
402
403
404
405
406
407
408
409
410
411
412
413
414			`mb`
415			`8`
416
417			`mb`
418			`0x00`
419	131	jt_eaton
420	135	jt_eaton
421			`mb_microbus`
422			`0x10`
423			`8`
424	131	jt_eaton
425
426	135	jt_eaton
427			`xmit_data`
428			`0x0`
429			`8`
430			`write-only`
431
432	131	jt_eaton
433	135	jt_eaton
434			`rcv_data`
435			`0x2`
436			`8`
437			`read-only`
438
439	131	jt_eaton
440
441	135	jt_eaton
442			`cntrl`
443			`0x4`
444			`8`
445			`read-write`
446
447	131	jt_eaton
448	135	jt_eaton
449			`status`
450			`0x6`
451			`8`
452			`read-only`
453
454	131	jt_eaton
455
456	135	jt_eaton
457	131	jt_eaton
458
459	135	jt_eaton
460	131	jt_eaton
461	135	jt_eaton
462	131	jt_eaton
463
464
465
466	135	jt_eaton