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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [xml/] [io_utimer_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_utimer
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
        
      
 
   little
   8
     
  
 
 

 
 
 

 
 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_utimer_def
    
  

 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_utimer_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_utimer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/io_utimer_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_utimer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 

       
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 
enable
wire
in

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 

 

 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   latch
   0x0
   8
   read-write
  
 
 
   count
   0x2
   8
   read-write
  
 
 
 
 
  
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [xml/] [io_utimer_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_utimer`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80	135	jt_eaton	`mb`
81
82
83
84
85
86
87			`rdata`
88
89			`rdata`
90			`wire`
91			`70`
92
93
94	131	jt_eaton
95	135	jt_eaton
96			`addr`
97
98			`addr`
99			`30`
100
101
102	131	jt_eaton
103	135	jt_eaton
104			`wdata`
105
106			`wdata`
107			`70`
108
109
110	131	jt_eaton
111
112	135	jt_eaton
113			`rd`
114
115			`rd`
116
117
118	131	jt_eaton
119	135	jt_eaton
120			`wr`
121
122			`wr`
123
124
125	131	jt_eaton
126	135	jt_eaton
127			`cs`
128
129			`cs`
130
131
132	131	jt_eaton
133	135	jt_eaton
134
135
136	131	jt_eaton
137	135	jt_eaton	`little`
138			`8`
139
140
141	131	jt_eaton
142
143	135	jt_eaton
144	131	jt_eaton
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151
152
153	133	jt_eaton
154	131	jt_eaton
155	135	jt_eaton
156			`gen_registers`
157			`102.1`
158			`:common:`
159			`none`
160			`tools/regtool/gen_registers`
161
162
163			`bus_intf`
164			`mb`
165
166
167			`dest_dir`
168			`../verilog`
169
170
171
172	131	jt_eaton
173	135	jt_eaton
174			`gen_verilog`
175			`104.0`
176			`none`
177			`:common:`
178			`tools/verilog/gen_verilog`
179
180
181			`destination`
182			`io_utimer_def`
183
184
185
186	131	jt_eaton
187
188	135	jt_eaton
189	131	jt_eaton
190
191	135	jt_eaton
192	131	jt_eaton
193	135	jt_eaton
194			`fs-common`
195	131	jt_eaton
196	135	jt_eaton
197
198			`../verilog/top.body`
199			`verilogSourcefragment`
200
201	131	jt_eaton
202
203	135	jt_eaton
204	131	jt_eaton
205	135	jt_eaton
206			`fs-sim`
207	131	jt_eaton
208	135	jt_eaton
209
210			`../verilog/copyright.v`
211			`verilogSourceinclude`
212
213	131	jt_eaton
214	135	jt_eaton
215
216			`../verilog/common/io_utimer_def`
217			`verilogSourcemodule`
218
219	131	jt_eaton
220	135	jt_eaton
221			`mb`
222			`../verilog/io_utimer_def_mb`
223			`verilogSourcemodule`
224
225	131	jt_eaton
226
227
228	135	jt_eaton
229	131	jt_eaton
230
231
232	135	jt_eaton
233			`fs-syn`
234	131	jt_eaton
235	135	jt_eaton
236
237			`../verilog/copyright.v`
238			`verilogSourceinclude`
239
240	131	jt_eaton
241
242	135	jt_eaton
243
244			`../verilog/common/io_utimer_def`
245			`verilogSourcemodule`
246
247	131	jt_eaton
248	135	jt_eaton
249			`mb`
250			`../verilog/io_utimer_def_mb`
251			`verilogSourcemodule`
252
253	131	jt_eaton
254
255
256	135	jt_eaton
257	131	jt_eaton
258
259
260	135	jt_eaton
261	131	jt_eaton
262
263
264
265	135	jt_eaton
266
267	131	jt_eaton
268	135	jt_eaton
269			`verilog`
270
271
272			`ipxact:library="Testbench"`
273			`ipxact:name="toolflow"`
274			`ipxact:version="verilog"/>`
275
276
277	131	jt_eaton
278
279
280
281
282	135	jt_eaton
283
284			`common:common:`
285	131	jt_eaton
286	135	jt_eaton	`Verilog`
287
288
289			`fs-common`
290
291
292	131	jt_eaton
293	135	jt_eaton
294			`sim:Simulation:`
295	131	jt_eaton
296	135	jt_eaton	`Verilog`
297
298
299			`fs-sim`
300
301
302	131	jt_eaton
303
304	135	jt_eaton
305			`syn:Synthesis:`
306	131	jt_eaton
307	135	jt_eaton	`Verilog`
308
309
310			`fs-syn`
311
312
313	131	jt_eaton
314
315
316	135	jt_eaton
317			`doc`
318
319
320			`ipxact:library="Testbench"`
321			`ipxact:name="toolflow"`
322			`ipxact:version="documentation"/>`
323
324			`:Documentation:`
325			`Verilog`
326
327	131	jt_eaton
328
329
330	135	jt_eaton
331	131	jt_eaton
332
333
334
335	135	jt_eaton
336	131	jt_eaton
337
338	135	jt_eaton	`enable`
339			`wire`
340			`in`
341
342	131	jt_eaton
343
344	135	jt_eaton
345			`clk`
346			`wire`
347			`in`
348
349	131	jt_eaton
350
351	135	jt_eaton	`reset`
352			`wire`
353			`in`
354
355	131	jt_eaton
356
357	135	jt_eaton	`cs`
358			`wire`
359			`in`
360
361	131	jt_eaton
362
363	135	jt_eaton	`rd`
364			`wire`
365			`in`
366
367	131	jt_eaton
368	135	jt_eaton	`wr`
369			`wire`
370			`in`
371
372	131	jt_eaton
373	135	jt_eaton
374			`addr`
375			`wire`
376			`in`
377			`30`
378
379
380
381			`wdata`
382			`wire`
383			`in`
384			`70`
385
386
387
388			`rdata`
389			`wire`
390			`out`
391			`70`
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408			`mb`
409			`8`
410
411			`mb`
412			`0x00`
413	131	jt_eaton
414	135	jt_eaton
415			`mb_microbus`
416			`0x10`
417			`8`
418	131	jt_eaton
419
420	135	jt_eaton
421			`latch`
422			`0x0`
423			`8`
424			`read-write`
425
426	131	jt_eaton
427	135	jt_eaton
428			`count`
429			`0x2`
430			`8`
431			`read-write`
432
433	131	jt_eaton
434
435
436
437	135	jt_eaton
438	131	jt_eaton
439
440	135	jt_eaton
441	131	jt_eaton
442	135	jt_eaton
443	131	jt_eaton
444
445
446
447
448
449	135	jt_eaton