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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [flash_memcontrl_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2100 300 1 0 0 in_port_vector.sym
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{
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T 2100 300 5 10 1 1 0 6 1 1
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refdes=wdata[15:0]
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}
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C 2100 700 1 0 0 in_port_vector.sym
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{
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T 2100 700 5 10 1 1 0 6 1 1
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refdes=memdb_in[15:0]
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}
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C 2100 1100 1 0 0 in_port_vector.sym
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{
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T 2100 1100 5 10 1 1 0 6 1 1
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refdes=cs[1:0]
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}
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C 2100 1500 1 0 0 in_port_vector.sym
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{
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T 2100 1500 5 10 1 1 0 6 1 1
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refdes=addr[ADDR_BITS-1:1]
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}
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C 2100 1900 1 0 0 in_port.sym
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{
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T 2100 1900 5 10 1 1 0 6 1 1
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refdes=wr
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}
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C 2100 2300 1 0 0 in_port.sym
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{
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T 2100 2300 5 10 1 1 0 6 1 1
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refdes=ub
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}
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C 2100 2700 1 0 0 in_port.sym
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{
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T 2100 2700 5 10 1 1 0 6 1 1
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refdes=stb
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}
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C 2100 3100 1 0 0 in_port.sym
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{
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T 2100 3100 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 2100 3500 1 0 0 in_port.sym
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{
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T 2100 3500 5 10 1 1 0 6 1 1
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refdes=rd
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}
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C 2100 3900 1 0 0 in_port.sym
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{
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T 2100 3900 5 10 1 1 0 6 1 1
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refdes=ramwait_in
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}
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C 2100 4300 1 0 0 in_port.sym
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{
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T 2100 4300 5 10 1 1 0 6 1 1
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refdes=lb
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}
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C 2100 4700 1 0 0 in_port.sym
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{
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T 2100 4700 5 10 1 1 0 6 1 1
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refdes=flashststs_in
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}
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C 2100 5100 1 0 0 in_port.sym
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{
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T 2100 5100 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 5900 300  1 0  0 out_port_vector.sym
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{
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T 6900 300 5  10 1 1 0 0 1 1
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refdes=rdata[15:0]
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}
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C 5900 700  1 0  0 out_port_vector.sym
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{
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T 6900 700 5  10 1 1 0 0 1 1
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refdes=memdb_out[15:0]
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}
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C 5900 1100  1 0  0 out_port_vector.sym
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{
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T 6900 1100 5  10 1 1 0 0 1 1
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refdes=memadr_out[ADDR_BITS-1:1]
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}
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C 5900 1500  1 0 0 out_port.sym
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{
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T 6900 1500 5  10 1 1 0 0 1 1
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refdes=wait_out
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}
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C 5900 1900  1 0 0 out_port.sym
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{
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T 6900 1900 5  10 1 1 0 0 1 1
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refdes=ramub_n_out
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}
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C 5900 2300  1 0 0 out_port.sym
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{
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T 6900 2300 5  10 1 1 0 0 1 1
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refdes=ramlb_n_out
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}
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C 5900 2700  1 0 0 out_port.sym
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{
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T 6900 2700 5  10 1 1 0 0 1 1
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refdes=ramcs_n_out
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}
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C 5900 3100  1 0 0 out_port.sym
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{
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T 6900 3100 5  10 1 1 0 0 1 1
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refdes=ramcre_out
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}
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C 5900 3500  1 0 0 out_port.sym
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{
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T 6900 3500 5  10 1 1 0 0 1 1
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refdes=ramclk_out
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}
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C 5900 3900  1 0 0 out_port.sym
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{
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T 6900 3900 5  10 1 1 0 0 1 1
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refdes=ramadv_n_out
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}
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C 5900 4300  1 0 0 out_port.sym
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{
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T 6900 4300 5  10 1 1 0 0 1 1
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refdes=memwr_n_out
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}
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C 5900 4700  1 0 0 out_port.sym
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{
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T 6900 4700 5  10 1 1 0 0 1 1
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refdes=memoe_n_out
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}
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C 5900 5100  1 0 0 out_port.sym
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{
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T 6900 5100 5  10 1 1 0 0 1 1
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refdes=memdb_oe
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}
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C 5900 5500  1 0 0 out_port.sym
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{
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T 6900 5500 5  10 1 1 0 0 1 1
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refdes=flashrp_n_out
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}
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C 5900 5900  1 0 0 out_port.sym
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{
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T 6900 5900 5  10 1 1 0 0 1 1
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refdes=flashcs_n_out
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}

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