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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sym/] [flash_memcontrl_def.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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B 300 0  4800 3300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 3450   5 10 1 1 0 0 1 1
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device=flash_memcontrl_def
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T 400 3650 5 10 1 1 0 0 1 1
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refdes=U?
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T 400 3800    0 10 0 1 0 0 1 1
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vendor=opencores.org
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T 400 3800    0 10 0 1 0 0 1 1
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library=logic
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T 400 3800    0 10 0 1 0 0 1 1
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component=flash_memcontrl
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T 400 3800    0 10 0 1 0 0 1 1
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version=def
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=wdata[15:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=memdb_in[15:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 10 1 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=cs[1:0]
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 10 1 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=addr[ADDR_BITS-1:1]
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 300 1000 0 1000 4 0 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=wr
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
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}
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P 300 1200 0 1200 4 0 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=ub
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
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P 300 1400 0 1400 4 0 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=stb
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T 400 1400 5 10 0 1 0 1 1 1
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pinseq=7
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}
64 
P 300 1600 0 1600 4 0 1
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{
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T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=reset
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T 400 1600 5 10 0 1 0 1 1 1
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pinseq=8
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}
71 
P 300 1800 0 1800 4 0 1
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{
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T 400 1800 5 10 1 1 0 1 1 1
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pinnumber=rd
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T 400 1800 5 10 0 1 0 1 1 1
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pinseq=9
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}
78 
P 300 2000 0 2000 4 0 1
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{
80 
T 400 2000 5 10 1 1 0 1 1 1
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pinnumber=ramwait_in
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T 400 2000 5 10 0 1 0 1 1 1
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pinseq=10
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}
85 
P 300 2200 0 2200 4 0 1
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{
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T 400 2200 5 10 1 1 0 1 1 1
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pinnumber=lb
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T 400 2200 5 10 0 1 0 1 1 1
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pinseq=11
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}
92 
P 300 2400 0 2400 4 0 1
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{
94 
T 400 2400 5 10 1 1 0 1 1 1
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pinnumber=flashststs_in
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T 400 2400 5 10 0 1 0 1 1 1
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pinseq=12
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}
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P 300 2600 0 2600 4 0 1
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{
101 
T 400 2600 5 10 1 1 0 1 1 1
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pinnumber=clk
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T 400 2600 5 10 0 1 0 1 1 1
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pinseq=13
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}
106 
P 5100 200 5400 200 10 1 1
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{
108 
T 5000 200 5  10 1 1 0 7 1 1
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pinnumber=rdata[15:0]
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T 5000 200 5  10 0 1 0 7 1 1
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pinseq=14
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}
113 
P 5100 400 5400 400 10 1 1
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{
115 
T 5000 400 5  10 1 1 0 7 1 1
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pinnumber=memdb_out[15:0]
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T 5000 400 5  10 0 1 0 7 1 1
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pinseq=15
119 
}
120 
P 5100 600 5400 600 10 1 1
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{
122 
T 5000 600 5  10 1 1 0 7 1 1
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pinnumber=memadr_out[ADDR_BITS-1:1]
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T 5000 600 5  10 0 1 0 7 1 1
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pinseq=16
126 
}
127 
P 5100 800 5400 800 4 0 1
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{
129 
T 5000 800 5  10 1 1 0 7 1 1
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pinnumber=wait_out
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T 5100 800 5  10 0 1 0 7 1 1
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pinseq=17
133 
}
134 
P 5100 1000 5400 1000 4 0 1
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{
136 
T 5000 1000 5  10 1 1 0 7 1 1
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pinnumber=ramub_n_out
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T 5100 1000 5  10 0 1 0 7 1 1
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pinseq=18
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}
141 
P 5100 1200 5400 1200 4 0 1
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{
143 
T 5000 1200 5  10 1 1 0 7 1 1
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pinnumber=ramlb_n_out
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T 5100 1200 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}
148 
P 5100 1400 5400 1400 4 0 1
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{
150 
T 5000 1400 5  10 1 1 0 7 1 1
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pinnumber=ramcs_n_out
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T 5100 1400 5  10 0 1 0 7 1 1
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pinseq=20
154 
}
155 
P 5100 1600 5400 1600 4 0 1
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{
157 
T 5000 1600 5  10 1 1 0 7 1 1
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pinnumber=ramcre_out
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T 5100 1600 5  10 0 1 0 7 1 1
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pinseq=21
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}
162 
P 5100 1800 5400 1800 4 0 1
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{
164 
T 5000 1800 5  10 1 1 0 7 1 1
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pinnumber=ramclk_out
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T 5100 1800 5  10 0 1 0 7 1 1
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pinseq=22
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}
169 
P 5100 2000 5400 2000 4 0 1
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{
171 
T 5000 2000 5  10 1 1 0 7 1 1
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pinnumber=ramadv_n_out
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T 5100 2000 5  10 0 1 0 7 1 1
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pinseq=23
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}
176 
P 5100 2200 5400 2200 4 0 1
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{
178 
T 5000 2200 5  10 1 1 0 7 1 1
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pinnumber=memwr_n_out
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T 5100 2200 5  10 0 1 0 7 1 1
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pinseq=24
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}
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P 5100 2400 5400 2400 4 0 1
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{
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T 5000 2400 5  10 1 1 0 7 1 1
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pinnumber=memoe_n_out
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T 5100 2400 5  10 0 1 0 7 1 1
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pinseq=25
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}
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P 5100 2600 5400 2600 4 0 1
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{
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T 5000 2600 5  10 1 1 0 7 1 1
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pinnumber=memdb_oe
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T 5100 2600 5  10 0 1 0 7 1 1
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pinseq=26
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}
197 
P 5100 2800 5400 2800 4 0 1
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{
199 
T 5000 2800 5  10 1 1 0 7 1 1
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pinnumber=flashrp_n_out
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T 5100 2800 5  10 0 1 0 7 1 1
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pinseq=27
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}
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P 5100 3000 5400 3000 4 0 1
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{
206 
T 5000 3000 5  10 1 1 0 7 1 1
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pinnumber=flashcs_n_out
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T 5100 3000 5  10 0 1 0 7 1 1
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pinseq=28
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}

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