OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sym/] [ps2_interface_def.sym] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  3400 2700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 2850   5 10 1 1 0 0 1 1
4 
device=ps2_interface_def
5 
T 400 3050 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 3200    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 3200    0 10 0 1 0 0 1 1
10 
library=logic
11 
T 400 3200    0 10 0 1 0 0 1 1
12 
component=ps2_interface
13 
T 400 3200    0 10 0 1 0 0 1 1
14 
version=def
15 
P 300 200 0 200 10 1 1
16 
{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=tx_data[7:0]
19 
T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 4 0 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=tx_write
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 4 0 1
30 
{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=rx_clear
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 4 0 1
37 
{
38 
T 400 800 5 10 1 1 0 1 1 1
39 
pinnumber=reset
40 
T 400 800 5 10 0 1 0 1 1 1
41 
pinseq=4
42 
}
43 
P 300 1000 0 1000 4 0 1
44 
{
45 
T 400 1000 5 10 1 1 0 1 1 1
46 
pinnumber=ps2_data_pad_in
47 
T 400 1000 5 10 0 1 0 1 1 1
48 
pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
51 
{
52 
T 400 1200 5 10 1 1 0 1 1 1
53 
pinnumber=ps2_clk_pad_in
54 
T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=clk
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 3700 200 4000 200 10 1 1
65 
{
66 
T 3600 200 5  10 1 1 0 7 1 1
67 
pinnumber=rx_data[7:0]
68 
T 3600 200 5  10 0 1 0 7 1 1
69 
pinseq=8
70 
}
71 
P 3700 400 4000 400 4 0 1
72 
{
73 
T 3600 400 5  10 1 1 0 7 1 1
74 
pinnumber=tx_buffer_empty
75 
T 3700 400 5  10 0 1 0 7 1 1
76 
pinseq=9
77 
}
78 
P 3700 600 4000 600 4 0 1
79 
{
80 
T 3600 600 5  10 1 1 0 7 1 1
81 
pinnumber=tx_ack_error
82 
T 3700 600 5  10 0 1 0 7 1 1
83 
pinseq=10
84 
}
85 
P 3700 800 4000 800 4 0 1
86 
{
87 
T 3600 800 5  10 1 1 0 7 1 1
88 
pinnumber=rx_read
89 
T 3700 800 5  10 0 1 0 7 1 1
90 
pinseq=11
91 
}
92 
P 3700 1000 4000 1000 4 0 1
93 
{
94 
T 3600 1000 5  10 1 1 0 7 1 1
95 
pinnumber=rx_parity_rcv
96 
T 3700 1000 5  10 0 1 0 7 1 1
97 
pinseq=12
98 
}
99 
P 3700 1200 4000 1200 4 0 1
100 
{
101 
T 3600 1200 5  10 1 1 0 7 1 1
102 
pinnumber=rx_parity_error
103 
T 3700 1200 5  10 0 1 0 7 1 1
104 
pinseq=13
105 
}
106 
P 3700 1400 4000 1400 4 0 1
107 
{
108 
T 3600 1400 5  10 1 1 0 7 1 1
109 
pinnumber=rx_parity_cal
110 
T 3700 1400 5  10 0 1 0 7 1 1
111 
pinseq=14
112 
}
113 
P 3700 1600 4000 1600 4 0 1
114 
{
115 
T 3600 1600 5  10 1 1 0 7 1 1
116 
pinnumber=rx_full
117 
T 3700 1600 5  10 0 1 0 7 1 1
118 
pinseq=15
119 
}
120 
P 3700 1800 4000 1800 4 0 1
121 
{
122 
T 3600 1800 5  10 1 1 0 7 1 1
123 
pinnumber=rx_frame_error
124 
T 3700 1800 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}
127 
P 3700 2000 4000 2000 4 0 1
128 
{
129 
T 3600 2000 5  10 1 1 0 7 1 1
130 
pinnumber=ps2_data_pad_oe
131 
T 3700 2000 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 3700 2200 4000 2200 4 0 1
135 
{
136 
T 3600 2200 5  10 1 1 0 7 1 1
137 
pinnumber=ps2_clk_pad_oe
138 
T 3700 2200 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}
141 
P 3700 2400 4000 2400 4 0 1
142 
{
143 
T 3600 2400 5  10 1 1 0 7 1 1
144 
pinnumber=busy
145 
T 3700 2400 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.