URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
disp_io
def.design
 
 
 
 

 

clk



 
 

reset



 
 

one_usec



 
 
 
 
    
      
         
    
 
    
      
      
    
 
 
 

 
 
 

 

cde_divider 

 6

 

 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`disp_io`
40			`def.design`
41	131	jt_eaton
42
43
44	133	jt_eaton
45	135	jt_eaton
46	133	jt_eaton
47	135	jt_eaton
48			`clk`
49
50
51
52	133	jt_eaton
53
54	135	jt_eaton
55			`reset`
56
57
58
59	133	jt_eaton
60
61	135	jt_eaton
62			`one_usec`
63
64
65
66	133	jt_eaton
67
68
69
70	135	jt_eaton
71
72
73
74	133	jt_eaton
75	135	jt_eaton
76
77
78
79	133	jt_eaton
80
81
82	135	jt_eaton
83	133	jt_eaton
84
85
86	135	jt_eaton
87	131	jt_eaton
88	135	jt_eaton
89			`cde_divider`
90
91			`6`
92
93	133	jt_eaton
94	135	jt_eaton
95	131	jt_eaton
96	135	jt_eaton
97	131	jt_eaton
98
99
100
101	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.design.xml] - Blame information for rev 135