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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
disp_io
def
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
          
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
          
      
  
 
 
 
 
 
 slave_enable
  
  
      
  
    
      
        enable
        enable
      
    
          
      
  
 
 
 
 
 
 
 

 
 
 
 

 
 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      disp_io_def
    
  

 
 
 

 
 
 
 
 

 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
       
 
 
              
              Hierarchical
                  Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
enable
wire
in

 
 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_def
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_def
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`disp_io`
40			`def`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59
60	131	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	131	jt_eaton
78
79
80	135	jt_eaton
81			`slave_enable`
82
83
84
85
86
87
88			`enable`
89			`enable`
90
91
92
93
94
95
96	131	jt_eaton
97
98
99
100
101	135	jt_eaton
102
103	131	jt_eaton
104
105
106
107	135	jt_eaton
108	133	jt_eaton
109	131	jt_eaton
110
111
112
113
114
115
116	135	jt_eaton
117			`gen_verilog`
118			`104.0`
119			`none`
120			`:common:`
121			`tools/verilog/gen_verilog`
122
123
124			`destination`
125			`disp_io_def`
126
127
128
129	131	jt_eaton
130
131
132	135	jt_eaton
133	131	jt_eaton
134
135
136
137
138	135	jt_eaton
139	131	jt_eaton
140
141	135	jt_eaton
142
143			`Hierarchical`
144
145
146
147
148
149
150
151
152
153			`Hierarchical`
154			`Hierarchical`
155
156
157
158
159
160			`verilog`
161
162
163			`ipxact:library="Testbench"`
164			`ipxact:name="toolflow"`
165			`ipxact:version="verilog"/>`
166
167
168
169
170
171
172
173
174			`common:common:`
175	131	jt_eaton
176	135	jt_eaton	`Verilog`
177
178
179			`fs-common`
180
181
182	131	jt_eaton
183
184	135	jt_eaton
185			`sim:Simulation:`
186	131	jt_eaton
187	135	jt_eaton	`Verilog`
188
189
190			`fs-sim`
191
192
193	131	jt_eaton
194
195	135	jt_eaton
196			`syn:Synthesis:`
197	131	jt_eaton
198	135	jt_eaton	`Verilog`
199
200
201			`fs-syn`
202
203
204	131	jt_eaton
205
206
207
208
209
210	135	jt_eaton
211			`doc`
212
213
214			`ipxact:library="Testbench"`
215			`ipxact:name="toolflow"`
216			`ipxact:version="documentation"/>`
217
218			`:Documentation:`
219			`Verilog`
220
221	131	jt_eaton
222
223
224	135	jt_eaton
225	131	jt_eaton
226
227
228	135	jt_eaton
229	131	jt_eaton
230	135	jt_eaton	`clk`
231			`wire`
232			`in`
233
234	131	jt_eaton
235
236	135	jt_eaton	`reset`
237			`wire`
238			`in`
239
240	131	jt_eaton
241
242	135	jt_eaton	`enable`
243			`wire`
244			`in`
245
246	131	jt_eaton
247
248
249	135	jt_eaton	`PosD`
250			`wire`
251			`in`
252			`150`
253
254	131	jt_eaton
255	135	jt_eaton	`PosL`
256			`wire`
257			`in`
258			`70`
259
260	131	jt_eaton
261	135	jt_eaton	`PosB`
262			`reg`
263			`out`
264			`30`
265
266	131	jt_eaton
267	135	jt_eaton	`PosS`
268			`reg`
269			`out`
270			`70`
271
272	131	jt_eaton
273	135	jt_eaton	`btn_pad_in`
274			`wire`
275			`in`
276			`30`
277
278	131	jt_eaton
279	135	jt_eaton	`sw_pad_in`
280			`wire`
281			`in`
282			`70`
283
284	131	jt_eaton
285	135	jt_eaton	`led_pad_out`
286			`reg`
287			`out`
288			`70`
289
290	131	jt_eaton
291	135	jt_eaton	`seg_pad_out`
292			`reg`
293			`out`
294			`60`
295
296	131	jt_eaton
297	135	jt_eaton	`dp_pad_out`
298			`reg`
299			`out`
300
301	131	jt_eaton
302	135	jt_eaton	`an_pad_out`
303			`reg`
304			`out`
305			`30`
306
307	131	jt_eaton
308	135	jt_eaton
309	131	jt_eaton
310	135	jt_eaton
311	131	jt_eaton
312	134	jt_eaton
313
314	135	jt_eaton
315	134	jt_eaton
316
317	135	jt_eaton
318			`fs-common`
319	134	jt_eaton
320	135	jt_eaton
321
322			`../verilog/top.body`
323			`verilogSourcefragment`
324
325	134	jt_eaton
326	135	jt_eaton
327	134	jt_eaton
328
329	135	jt_eaton
330			`fs-sim`
331	134	jt_eaton
332	135	jt_eaton
333
334			`../verilog/copyright`
335			`verilogSourceinclude`
336
337	134	jt_eaton
338	135	jt_eaton
339
340			`../verilog/common/disp_io_def`
341			`verilogSourcemodule`
342
343	134	jt_eaton
344
345	135	jt_eaton
346	134	jt_eaton
347
348
349
350	135	jt_eaton
351			`fs-syn`
352	134	jt_eaton
353	135	jt_eaton
354
355			`../verilog/copyright`
356			`verilogSourceinclude`
357
358	134	jt_eaton
359	135	jt_eaton
360
361			`../verilog/common/disp_io_def`
362			`verilogSourcemodule`
363
364	134	jt_eaton
365	135	jt_eaton
366	134	jt_eaton
367
368
369
370	135	jt_eaton
371	134	jt_eaton
372
373	135	jt_eaton
374
375
376
377
378
379