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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_jtag.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
disp_io
jtag
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
          
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
  slave_enable
  
  
      
  
    
      
        enable
        enable
      
    
        
      
  
 
 
 
 
 
 
 
 
 
 btn_pad
  
  
      
  
    
      
        pad_in
        btn_pad_in
      
    
        
      
  
 
 
 
  sw_pad
  
  
      
  
    
      
        pad_in
        sw_pad_in
      
    
        
      
  
  
 
 
 
  led_pad
  
  
      
  
    
      
        pad_out
        led_pad_out
      
    
        
      
  
 
 
 
 
  seg_pad
  
  
      
  
    
      
        pad_out
        seg_pad_out
      
    
        
      
  
 
 
 
 
 
 
   dp_pad
  
  
      
  
    
      
        pad_out
        dp_pad_out
      
    
        
      
  
 
 
 
 
 
  an_pad
  
  
      
  
    
      
        pad_out
        an_pad_out
      
    
        
      
  
 
 
 
 
 
 

 
 
  jtag
  
  
      
  
 
 
    
 
      
        test_logic_reset
        test_logic_reset_o
      
 
      
        capture_dr
        capture_dr_o
      
 
      
        shift_dr
        
        shift_dr_o
        
      
 
      
        update_dr_clk
        update_dr_clk_o
       
      
 
      
        tdi
        tdi_o
      
      
 
      
      tdo
      
      tdo_i
      
      
 
      
      select
      
      select_o
      
      
 
      
      shiftcapture_dr_clk
      
      shiftcapture_dr_clk_o
      
      
 
    
 
 
        
      
 
 
 
  
 
  
 
 
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      disp_io_jtag
    
  

 
 
 

 
 
 
 
 
 
 

 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
       
 
 
              
              Hierarchical
                     Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 
 
 
 
 
PosD
wire
in
150

 
PosL
wire
in
70

 
PosB
reg
out
30

 
PosS
reg
out
70

 
btn_pad_in
wire
in
30

 
sw_pad_in
wire
in
70

 
led_pad_out
reg
out
70

 
seg_pad_out
reg
out
60

 
dp_pad_out
reg
out

 
an_pad_out
reg
out
30

 

 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.jtag
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_jtag
        verilogSourcemodule
      
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/disp_io_jtag
        verilogSourcemodule
      
 
    
 
 
  
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [xml/] [disp_io_jtag.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	134	jt_eaton
2	133	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	133	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`disp_io`
40			`jtag`
41	133	jt_eaton
42
43	135	jt_eaton
44	133	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59
60	133	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	133	jt_eaton
78
79
80	135	jt_eaton	`slave_enable`
81
82
83
84
85
86
87			`enable`
88			`enable`
89
90
91
92
93
94
95	133	jt_eaton
96
97
98
99
100
101	135	jt_eaton
102	133	jt_eaton
103	135	jt_eaton	`btn_pad`
104
105
106
107
108
109
110			`pad_in`
111			`btn_pad_in`
112
113
114
115
116
117
118	133	jt_eaton
119
120	135	jt_eaton	`sw_pad`
121
122
123
124
125
126
127			`pad_in`
128			`sw_pad_in`
129
130
131
132
133
134
135	133	jt_eaton
136
137
138	135	jt_eaton	`led_pad`
139
140
141
142
143
144
145			`pad_out`
146			`led_pad_out`
147
148
149
150
151
152
153
154	133	jt_eaton
155
156	135	jt_eaton	`seg_pad`
157
158
159
160
161
162
163			`pad_out`
164			`seg_pad_out`
165
166
167
168
169
170
171
172	133	jt_eaton
173
174	135	jt_eaton
175
176			`dp_pad`
177
178
179
180
181
182
183			`pad_out`
184			`dp_pad_out`
185
186
187
188
189
190
191
192	133	jt_eaton
193
194
195	135	jt_eaton	`an_pad`
196
197
198
199
200
201
202			`pad_out`
203			`an_pad_out`
204
205
206
207
208
209
210
211	133	jt_eaton
212
213
214	135	jt_eaton
215
216	133	jt_eaton
217	135	jt_eaton
218			`jtag`
219
220
221
222
223	133	jt_eaton
224
225	135	jt_eaton
226	133	jt_eaton
227	135	jt_eaton
228			`test_logic_reset`
229			`test_logic_reset_o`
230
231
232
233			`capture_dr`
234			`capture_dr_o`
235
236
237
238			`shift_dr`
239
240			`shift_dr_o`
241
242
243
244
245			`update_dr_clk`
246			`update_dr_clk_o`
247
248
249
250
251			`tdi`
252			`tdi_o`
253
254
255
256
257			`tdo`
258
259			`tdo_i`
260
261
262
263
264			`select`
265
266			`select_o`
267
268
269
270
271			`shiftcapture_dr_clk`
272
273			`shiftcapture_dr_clk_o`
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298			`gen_verilog`
299			`104.0`
300			`none`
301			`:common:`
302			`tools/verilog/gen_verilog`
303
304
305			`destination`
306			`disp_io_jtag`
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326			`Hierarchical`
327
328
329
330
331
332
333
334
335
336
337			`Hierarchical`
338			`Hierarchical`
339
340
341
342
343
344			`verilog`
345
346
347			`ipxact:library="Testbench"`
348			`ipxact:name="toolflow"`
349			`ipxact:version="verilog"/>`
350
351
352
353
354
355
356
357
358			`common:common:`
359	133	jt_eaton
360	135	jt_eaton	`Verilog`
361
362
363			`fs-common`
364
365
366	133	jt_eaton
367
368	135	jt_eaton
369			`sim:Simulation:`
370	133	jt_eaton
371	135	jt_eaton	`Verilog`
372
373
374			`fs-sim`
375
376
377	133	jt_eaton
378
379	135	jt_eaton
380			`syn:Synthesis:`
381	133	jt_eaton
382	135	jt_eaton	`Verilog`
383
384
385			`fs-syn`
386
387
388	133	jt_eaton
389
390
391
392
393
394	135	jt_eaton
395			`doc`
396
397
398			`ipxact:library="Testbench"`
399			`ipxact:name="toolflow"`
400			`ipxact:version="documentation"/>`
401
402			`:Documentation:`
403			`Verilog`
404
405	133	jt_eaton
406
407
408	135	jt_eaton
409	133	jt_eaton
410
411
412	135	jt_eaton
413	133	jt_eaton
414	135	jt_eaton	`clk`
415			`wire`
416			`in`
417
418	133	jt_eaton
419
420	135	jt_eaton	`reset`
421			`wire`
422			`in`
423
424	133	jt_eaton
425
426
427	135	jt_eaton	`enable`
428			`wire`
429			`in`
430
431	133	jt_eaton
432
433
434
435	135	jt_eaton
436			`PosD`
437			`wire`
438			`in`
439			`150`
440
441	133	jt_eaton
442	135	jt_eaton	`PosL`
443			`wire`
444			`in`
445			`70`
446
447	133	jt_eaton
448	135	jt_eaton	`PosB`
449			`reg`
450			`out`
451			`30`
452
453	133	jt_eaton
454	135	jt_eaton	`PosS`
455			`reg`
456			`out`
457			`70`
458
459	133	jt_eaton
460	135	jt_eaton	`btn_pad_in`
461			`wire`
462			`in`
463			`30`
464
465	133	jt_eaton
466	135	jt_eaton	`sw_pad_in`
467			`wire`
468			`in`
469			`70`
470
471	133	jt_eaton
472	135	jt_eaton	`led_pad_out`
473			`reg`
474			`out`
475			`70`
476
477	133	jt_eaton
478	135	jt_eaton	`seg_pad_out`
479			`reg`
480			`out`
481			`60`
482
483	133	jt_eaton
484	135	jt_eaton	`dp_pad_out`
485			`reg`
486			`out`
487
488	133	jt_eaton
489	135	jt_eaton	`an_pad_out`
490			`reg`
491			`out`
492			`30`
493
494	133	jt_eaton
495	135	jt_eaton
496	134	jt_eaton
497	135	jt_eaton
498	134	jt_eaton
499
500
501	135	jt_eaton
502	134	jt_eaton
503
504	135	jt_eaton
505			`fs-common`
506	134	jt_eaton
507	135	jt_eaton
508
509			`../verilog/top.jtag`
510			`verilogSourcefragment`
511
512	134	jt_eaton
513	135	jt_eaton
514	134	jt_eaton
515
516	135	jt_eaton
517			`fs-sim`
518	134	jt_eaton
519	135	jt_eaton
520
521			`../verilog/copyright`
522			`verilogSourceinclude`
523
524	134	jt_eaton
525	135	jt_eaton
526
527			`../verilog/common/disp_io_jtag`
528			`verilogSourcemodule`
529
530	134	jt_eaton
531
532	135	jt_eaton
533	134	jt_eaton
534
535
536
537	135	jt_eaton
538			`fs-syn`
539	134	jt_eaton
540	135	jt_eaton
541
542			`../verilog/copyright`
543			`verilogSourceinclude`
544
545	134	jt_eaton
546	135	jt_eaton
547
548			`../verilog/common/disp_io_jtag`
549			`verilogSourcemodule`
550
551	134	jt_eaton
552	135	jt_eaton
553	134	jt_eaton
554
555	135	jt_eaton
556
557
558
559
560
561
562
563
564