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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
disp_io
def_tb
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      disp_io_def_tb
    
  

 
 
 
 
 

 
 
 
 
 

 
       
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="disp_io"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="disp_io"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
      
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/disp_io_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/disp_io_def_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 

 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`disp_io`
40			`def_tb`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45
46
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`disp_io_def_tb`
58
59
60
61	131	jt_eaton
62
63
64
65
66	135	jt_eaton
67	131	jt_eaton
68
69
70
71
72	135	jt_eaton
73	131	jt_eaton
74	135	jt_eaton
75	131	jt_eaton
76	135	jt_eaton
77			`Params`
78
79
80			`ipxact:library="logic"`
81			`ipxact:name="disp_io"`
82			`ipxact:version="def_dut.params"/>`
83
84
85	131	jt_eaton
86
87
88
89	135	jt_eaton
90			`Bfm`
91
92			`ipxact:library="logic"`
93			`ipxact:name="disp_io"`
94			`ipxact:version="bfm.design"/>`
95
96	131	jt_eaton
97
98	135	jt_eaton
99			`icarus`
100
101
102			`ipxact:library="Testbench"`
103			`ipxact:name="toolflow"`
104			`ipxact:version="icarus"/>`
105
106
107	131	jt_eaton
108
109
110
111	135	jt_eaton
112			`common:common:`
113			`Verilog`
114
115
116			`fs-common`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`sim:Simulation:`
122			`Verilog`
123
124
125			`fs-sim`
126
127
128	131	jt_eaton
129
130	135	jt_eaton
131			`lint:Lint:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138	131	jt_eaton
139
140
141
142	135	jt_eaton
143	131	jt_eaton
144	135	jt_eaton
145	131	jt_eaton
146
147	135	jt_eaton
148	131	jt_eaton
149	135	jt_eaton
150			`fs-common`
151	131	jt_eaton
152	135	jt_eaton
153
154			`../verilog/tb.ext`
155			`verilogSourcefragment`
156
157	131	jt_eaton
158
159	135	jt_eaton
160	131	jt_eaton
161
162
163	135	jt_eaton
164			`fs-sim`
165	131	jt_eaton
166	135	jt_eaton
167
168			`../verilog/common/disp_io_def_tb`
169			`verilogSourcemodule`
170
171	131	jt_eaton
172
173
174	135	jt_eaton
175	131	jt_eaton
176
177	135	jt_eaton
178			`fs-lint`
179	131	jt_eaton
180	135	jt_eaton
181
182			`../verilog/common/disp_io_def_tb`
183			`verilogSourcemodule`
184
185	131	jt_eaton
186
187	135	jt_eaton
188	131	jt_eaton
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195
196	135	jt_eaton
197	131	jt_eaton
198
199
200

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_def_tb.xml] - Blame information for rev 135