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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_jtag_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
disp_io
jtag_tb
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      disp_io_jtag_tb
    
  

 
 
 
 
 

 
 
 
 
 

 
       
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="disp_io"
                                   ipxact:version="jtag_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="disp_io"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              Jtag_Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="disp_io"
                                   ipxact:version="jtag_bfm.design"/>
              
 
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
      
 
 

    JTAG_MODEL_SIZE4
    JTAG_MODEL_DIVCNT4'h4

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/disp_io_jtag_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/disp_io_jtag_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 

 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	133	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`disp_io`
40			`jtag_tb`
41	133	jt_eaton
42
43	135	jt_eaton
44	133	jt_eaton
45
46
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`disp_io_jtag_tb`
58
59
60
61	133	jt_eaton
62
63
64
65
66	135	jt_eaton
67	133	jt_eaton
68
69
70
71
72	135	jt_eaton
73	133	jt_eaton
74	135	jt_eaton
75	133	jt_eaton
76	135	jt_eaton
77			`Params`
78
79
80			`ipxact:library="logic"`
81			`ipxact:name="disp_io"`
82			`ipxact:version="jtag_dut.params"/>`
83
84
85	133	jt_eaton
86
87
88
89	135	jt_eaton
90			`Bfm`
91
92			`ipxact:library="logic"`
93			`ipxact:name="disp_io"`
94			`ipxact:version="bfm.design"/>`
95
96	133	jt_eaton
97
98	135	jt_eaton
99			`Jtag_Bfm`
100
101			`ipxact:library="logic"`
102			`ipxact:name="disp_io"`
103			`ipxact:version="jtag_bfm.design"/>`
104
105	133	jt_eaton
106
107
108
109	135	jt_eaton
110			`icarus`
111
112
113			`ipxact:library="Testbench"`
114			`ipxact:name="toolflow"`
115			`ipxact:version="icarus"/>`
116
117
118	133	jt_eaton
119
120
121
122	135	jt_eaton
123			`common:common:`
124			`Verilog`
125
126
127			`fs-common`
128
129
130	133	jt_eaton
131	135	jt_eaton
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139	133	jt_eaton
140
141	135	jt_eaton
142			`lint:Lint:`
143			`Verilog`
144
145
146			`fs-sim`
147
148
149	133	jt_eaton
150
151
152
153	135	jt_eaton
154	133	jt_eaton
155
156	135	jt_eaton
157			`JTAG_MODEL_SIZE4`
158			`JTAG_MODEL_DIVCNT4'h4`
159
160	133	jt_eaton
161
162
163
164	135	jt_eaton
165	133	jt_eaton
166
167	135	jt_eaton
168	133	jt_eaton
169	135	jt_eaton
170			`fs-common`
171	133	jt_eaton
172	135	jt_eaton
173
174			`../verilog/tb.ext`
175			`verilogSourcefragment`
176
177	133	jt_eaton
178
179	135	jt_eaton
180	133	jt_eaton
181
182
183	135	jt_eaton
184			`fs-sim`
185	133	jt_eaton
186	135	jt_eaton
187
188			`../verilog/common/disp_io_jtag_tb`
189			`verilogSourcemodule`
190
191	133	jt_eaton
192
193
194	135	jt_eaton
195	133	jt_eaton
196
197	135	jt_eaton
198			`fs-lint`
199	133	jt_eaton
200	135	jt_eaton
201
202			`../verilog/common/disp_io_jtag_tb`
203			`verilogSourcemodule`
204
205	133	jt_eaton
206
207	135	jt_eaton
208	133	jt_eaton
209
210
211
212	135	jt_eaton
213	133	jt_eaton
214
215
216	135	jt_eaton
217	133	jt_eaton
218
219
220

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [xml/] [disp_io_jtag_tb.xml] - Blame information for rev 135