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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
flash_memcontrl
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
 
        
      
 
 
  
 
 
 
 
 slave_reset
  
  
      
  
 
    
      
        reset
        reset
      
    
 
        
      
 
 
  
 
 
 

 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      flash_memcontrl_def
    
  

 
 
 

 
 
 

 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
       
 
              
              Hierarchical
                  Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
addr
wire
in
ADDR_BITS-11

 
wdata
wire
in
150

 
cs
wire
in
10

 
rd
wire
in

 
wr
wire
in

 
stb
wire
in

 
ub
wire
in

 
lb
wire
in

 
wait_out
reg
out

 
rdata
wire
out
150

 
memadr_out
reg
out
ADDR_BITS-11

 
memdb_out
reg
out
150

 
memdb_oe
reg
out

 
memdb_in
wire
in
150

 
memoe_n_out
reg
out

 
memwr_n_out
reg
out

 
ramadv_n_out
reg
out

 
ramclk_out
reg
out

 
ramub_n_out
reg
out

 
ramlb_n_out
reg
out

 
ramcs_n_out
reg
out

 
ramcre_out
reg
out

 
ramwait_in
wire
in

 
flashcs_n_out
reg
out

 
flashrp_n_out
reg
out

 
flashststs_in
wire
in

 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/flash_memcontrl_def
        verilogSourcemodule
      
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/flash_memcontrl_def
        verilogSourcemodule
      
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`flash_memcontrl`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60	131	jt_eaton
61
62	135	jt_eaton
63	131	jt_eaton
64	135	jt_eaton
65	131	jt_eaton
66
67	135	jt_eaton	`slave_reset`
68
69
70
71
72	131	jt_eaton
73	135	jt_eaton
74
75			`reset`
76			`reset`
77
78
79
80
81
82	131	jt_eaton
83
84	135	jt_eaton
85	131	jt_eaton
86	135	jt_eaton
87	131	jt_eaton
88	135	jt_eaton
89	131	jt_eaton
90
91	135	jt_eaton
92	131	jt_eaton
93	135	jt_eaton
94			`gen_verilog`
95			`104.0`
96			`none`
97			`:common:`
98			`tools/verilog/gen_verilog`
99
100
101			`destination`
102			`flash_memcontrl_def`
103
104
105
106	131	jt_eaton
107
108
109	135	jt_eaton
110	131	jt_eaton
111
112
113	135	jt_eaton
114	131	jt_eaton
115	135	jt_eaton
116
117			`Hierarchical`
118
119
120
121
122
123
124
125
126
127			`Hierarchical`
128			`Hierarchical`
129
130
131
132
133			`verilog`
134
135
136			`ipxact:library="Testbench"`
137			`ipxact:name="toolflow"`
138			`ipxact:version="verilog"/>`
139
140
141
142
143
144
145
146
147			`common:common:`
148	131	jt_eaton
149	135	jt_eaton	`Verilog`
150
151
152			`fs-common`
153
154
155	131	jt_eaton
156
157	135	jt_eaton
158			`sim:Simulation:`
159			`Verilog`
160
161
162			`fs-sim`
163
164
165	131	jt_eaton
166	135	jt_eaton
167			`syn:Synthesis:`
168			`Verilog`
169
170
171			`fs-sim`
172
173
174	131	jt_eaton
175
176
177
178
179	135	jt_eaton
180			`doc`
181
182
183			`ipxact:library="Testbench"`
184			`ipxact:name="toolflow"`
185			`ipxact:version="documentation"/>`
186
187			`:Documentation:`
188			`Verilog`
189
190	131	jt_eaton
191
192
193	135	jt_eaton
194	131	jt_eaton
195
196
197
198
199	135	jt_eaton
200	131	jt_eaton
201
202	135	jt_eaton	`addr`
203			`wire`
204			`in`
205			`ADDR_BITS-11`
206
207	131	jt_eaton
208	135	jt_eaton	`wdata`
209			`wire`
210			`in`
211			`150`
212
213	131	jt_eaton
214	135	jt_eaton	`cs`
215			`wire`
216			`in`
217			`10`
218
219	131	jt_eaton
220	135	jt_eaton	`rd`
221			`wire`
222			`in`
223
224	131	jt_eaton
225	135	jt_eaton	`wr`
226			`wire`
227			`in`
228
229	131	jt_eaton
230	135	jt_eaton	`stb`
231			`wire`
232			`in`
233
234	131	jt_eaton
235	135	jt_eaton	`ub`
236			`wire`
237			`in`
238
239	131	jt_eaton
240	135	jt_eaton	`lb`
241			`wire`
242			`in`
243
244	131	jt_eaton
245	135	jt_eaton	`wait_out`
246			`reg`
247			`out`
248
249	131	jt_eaton
250	135	jt_eaton	`rdata`
251			`wire`
252			`out`
253			`150`
254
255	131	jt_eaton
256	135	jt_eaton	`memadr_out`
257			`reg`
258			`out`
259			`ADDR_BITS-11`
260
261	131	jt_eaton
262	135	jt_eaton	`memdb_out`
263			`reg`
264			`out`
265			`150`
266
267	131	jt_eaton
268	135	jt_eaton	`memdb_oe`
269			`reg`
270			`out`
271
272	131	jt_eaton
273	135	jt_eaton	`memdb_in`
274			`wire`
275			`in`
276			`150`
277
278	131	jt_eaton
279	135	jt_eaton	`memoe_n_out`
280			`reg`
281			`out`
282
283	131	jt_eaton
284	135	jt_eaton	`memwr_n_out`
285			`reg`
286			`out`
287
288	131	jt_eaton
289	135	jt_eaton	`ramadv_n_out`
290			`reg`
291			`out`
292
293	131	jt_eaton
294	135	jt_eaton	`ramclk_out`
295			`reg`
296			`out`
297
298	131	jt_eaton
299	135	jt_eaton	`ramub_n_out`
300			`reg`
301			`out`
302
303	131	jt_eaton
304	135	jt_eaton	`ramlb_n_out`
305			`reg`
306			`out`
307
308	131	jt_eaton
309	135	jt_eaton	`ramcs_n_out`
310			`reg`
311			`out`
312
313	131	jt_eaton
314	135	jt_eaton	`ramcre_out`
315			`reg`
316			`out`
317
318	131	jt_eaton
319	135	jt_eaton	`ramwait_in`
320			`wire`
321			`in`
322
323	131	jt_eaton
324	135	jt_eaton	`flashcs_n_out`
325			`reg`
326			`out`
327
328	131	jt_eaton
329	135	jt_eaton	`flashrp_n_out`
330			`reg`
331			`out`
332
333	131	jt_eaton
334	135	jt_eaton	`flashststs_in`
335			`wire`
336			`in`
337
338	131	jt_eaton
339	135	jt_eaton
340	131	jt_eaton
341	135	jt_eaton
342	131	jt_eaton
343
344
345
346	135	jt_eaton
347	131	jt_eaton
348	135	jt_eaton
349			`fs-common`
350	131	jt_eaton
351	135	jt_eaton
352
353			`../verilog/top.body`
354			`verilogSourcefragment`
355
356	131	jt_eaton
357	135	jt_eaton
358	131	jt_eaton
359
360	135	jt_eaton
361			`fs-sim`
362	134	jt_eaton
363	135	jt_eaton
364
365			`../verilog/copyright`
366			`verilogSourceinclude`
367
368	134	jt_eaton
369	135	jt_eaton
370
371			`../verilog/common/flash_memcontrl_def`
372			`verilogSourcemodule`
373
374	134	jt_eaton
375	135	jt_eaton
376	134	jt_eaton
377
378
379	135	jt_eaton
380			`fs-syn`
381	134	jt_eaton
382	135	jt_eaton
383
384			`../verilog/copyright`
385			`verilogSourceinclude`
386
387	134	jt_eaton
388	135	jt_eaton
389
390			`../verilog/common/flash_memcontrl_def`
391			`verilogSourcemodule`
392
393	134	jt_eaton
394	135	jt_eaton
395	134	jt_eaton
396
397
398
399
400	135	jt_eaton
401	134	jt_eaton
402
403
404
405
406
407
408
409
410	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [rtl/] [xml/] [flash_memcontrl_def.xml] - Blame information for rev 135