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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_byte.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
micro_bus
byte
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
 
 
        
      
 
 
  
 
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
 master_enable
  
  
      
  
 
    
      
        enable
        enable
      
    
 
        
      
 
  
 
 
 
 
 
 
 
 
 
 cpu
  
  
      
  
    
      
        addr
        addr_in
        150
        
      
      
        rdata
        rdata_out
        reg
        70
        
      
 
 
 
      
        wdata
        wdata_in
        70
        
      
 
 
      
        wr
        wr_in
        
      
 
 
      
        rd
        rd_in
        
      
 
 
 
 
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 mem
  
  
      
  
 
    
 
      
        addr
        mem_addr
        150
        
      
 
      
        cs
        mem_cs
        reg
        40
        
      
 
      
        wdata
        mem_wdata
        150
        
      
 
      
        rdata
        mem_rdata
        470
        
      
 
 
      
        wait
        mem_wait
        10
        
      
 
 
      
        rd
        mem_rd
        
      
 
      
        wr
        mem_wr
        
      
 
    
 
        
      
 
 
  
 
 
 
 
 
 
 

 
 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      micro_bus_byte
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.byte
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/micro_bus_byte
        verilogSourcemodule
      
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/micro_bus_byte
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 

 
 
 
      
 
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_byte.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`micro_bus`
40			`byte`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57	131	jt_eaton
58	135	jt_eaton
59
60
61	131	jt_eaton
62
63	135	jt_eaton
64	131	jt_eaton
65	135	jt_eaton
66	131	jt_eaton
67
68	135	jt_eaton	`slave_reset`
69
70
71
72
73
74
75			`reset`
76			`reset`
77
78
79
80
81
82
83	131	jt_eaton
84
85	135	jt_eaton
86			`master_enable`
87
88
89
90
91	131	jt_eaton
92	135	jt_eaton
93
94			`enable`
95			`enable`
96
97
98
99
100
101	131	jt_eaton
102	135	jt_eaton
103	131	jt_eaton
104	135	jt_eaton
105	131	jt_eaton
106
107
108
109
110
111
112	135	jt_eaton	`cpu`
113
114
115
116
117
118
119			`addr`
120			`addr_in`
121			`150`
122
123
124
125			`rdata`
126			`rdata_out`
127			`reg`
128			`70`
129
130
131	131	jt_eaton
132
133
134	135	jt_eaton
135			`wdata`
136			`wdata_in`
137			`70`
138
139
140	131	jt_eaton
141
142	135	jt_eaton
143			`wr`
144			`wr_in`
145
146
147	131	jt_eaton
148
149	135	jt_eaton
150			`rd`
151			`rd_in`
152
153
154	131	jt_eaton
155
156
157
158	135	jt_eaton
159
160
161
162	131	jt_eaton
163
164	135	jt_eaton
165	131	jt_eaton
166	135	jt_eaton
167	131	jt_eaton
168
169
170	135	jt_eaton
171	131	jt_eaton
172	135	jt_eaton	`mem`
173
174
175
176
177
178
179	131	jt_eaton
180	135	jt_eaton
181			`addr`
182			`mem_addr`
183			`150`
184
185
186	131	jt_eaton
187	135	jt_eaton
188			`cs`
189			`mem_cs`
190			`reg`
191			`40`
192
193
194	131	jt_eaton
195	135	jt_eaton
196			`wdata`
197			`mem_wdata`
198			`150`
199
200
201	131	jt_eaton
202	135	jt_eaton
203			`rdata`
204			`mem_rdata`
205			`470`
206
207
208	131	jt_eaton
209
210	135	jt_eaton
211			`wait`
212			`mem_wait`
213			`10`
214
215
216	131	jt_eaton
217
218	135	jt_eaton
219			`rd`
220			`mem_rd`
221
222
223	131	jt_eaton
224	135	jt_eaton
225			`wr`
226			`mem_wr`
227
228
229	131	jt_eaton
230	135	jt_eaton
231
232
233
234
235	131	jt_eaton
236	135	jt_eaton
237	131	jt_eaton
238	135	jt_eaton
239	131	jt_eaton
240
241
242
243
244	135	jt_eaton
245	131	jt_eaton
246
247
248	135	jt_eaton
249	131	jt_eaton
250
251	135	jt_eaton
252			`gen_verilog`
253			`104.0`
254			`none`
255			`:common:`
256			`tools/verilog/gen_verilog`
257
258
259			`destination`
260			`micro_bus_byte`
261
262
263			`dest_dir`
264			`../verilog`
265
266
267
268	131	jt_eaton
269
270
271
272	135	jt_eaton
273	131	jt_eaton
274
275	135	jt_eaton
276	131	jt_eaton
277	135	jt_eaton
278			`fs-common`
279	131	jt_eaton
280	135	jt_eaton
281
282			`../verilog/top.body.byte`
283			`verilogSourcefragment`
284
285	131	jt_eaton
286	135	jt_eaton
287	131	jt_eaton
288
289
290	135	jt_eaton
291			`fs-sim`
292	131	jt_eaton
293	135	jt_eaton
294
295			`../verilog/copyright.v`
296			`verilogSourceinclude`
297
298	131	jt_eaton
299	135	jt_eaton
300
301			`../verilog/common/micro_bus_byte`
302			`verilogSourcemodule`
303
304	131	jt_eaton
305
306	135	jt_eaton
307	131	jt_eaton
308
309
310	135	jt_eaton
311			`fs-syn`
312	131	jt_eaton
313	135	jt_eaton
314
315			`../verilog/copyright.v`
316			`verilogSourceinclude`
317
318	131	jt_eaton
319
320	135	jt_eaton
321
322			`../verilog/common/micro_bus_byte`
323			`verilogSourcemodule`
324
325	131	jt_eaton
326
327
328	135	jt_eaton
329	131	jt_eaton
330
331
332
333	135	jt_eaton
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348			`verilog`
349
350
351			`ipxact:library="Testbench"`
352			`ipxact:name="toolflow"`
353			`ipxact:version="verilog"/>`
354
355
356
357
358
359
360
361
362			`common:common:`
363	131	jt_eaton
364	135	jt_eaton	`Verilog`
365
366
367			`fs-common`
368
369
370	131	jt_eaton
371	135	jt_eaton
372			`sim:Simulation:`
373	131	jt_eaton
374	135	jt_eaton	`Verilog`
375
376
377			`fs-sim`
378
379
380	131	jt_eaton
381
382
383	135	jt_eaton
384			`syn:Synthesis:`
385	131	jt_eaton
386	135	jt_eaton	`Verilog`
387
388
389			`fs-syn`
390
391
392	131	jt_eaton
393
394	135	jt_eaton
395			`doc`
396
397
398			`ipxact:library="Testbench"`
399			`ipxact:name="toolflow"`
400			`ipxact:version="documentation"/>`
401
402			`:Documentation:`
403			`Verilog`
404
405	131	jt_eaton
406
407	135	jt_eaton
408	131	jt_eaton
409
410
411
412
413
414
415
416	135	jt_eaton
417	131	jt_eaton
418
419
420
421
422
423
424
425	135	jt_eaton