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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
logic
serial_rcvr
 
2
_
_
_
VARIANT
 

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 
  
 
         
            default
            def
            
            WIDTH8
            SIZE4
            SAMPLE4'b0111
            START_VALUE1'b0
            STOP_VALUE1'b1
           
          
 
 
 
         
            fifo
            fifo
            
            WIDTH8
            SIZE4
            SAMPLE4'b0111
            START_VALUE1'b0
            STOP_VALUE1'b1
            RX_FIFO_SIZE4
            RX_FIFO_WORDS16
           
          
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 
serial_rcvr/sim
 
 
 
 

 
 
 

serial_rcvr_def_tb
def_tb
default

    PERIOD40
    TIMEOUT100000


  
  serial_rcvr_defTB.test.dut
  


  icaruscoverage


 
 
 
 
 

serial_rcvr_fifo_tb
fifo_tb
fifo

    PERIOD40
    TIMEOUT1000


  
  serial_rcvr_fifo
  TB.test.dut
  


  icaruscoverage


 
 
 
 
 
 

serial_rcvr_def_lint
def_lint
default

  rtl_check


 
 
 

serial_rcvr_fifo_lint
fifo_lint
fifo

  rtl_check


 

 
 
 
 
 

 

default
default
serial_rcvr_def_lint

 
 
 

fifo_default
fifo
serial_rcvr_fifo_lint

 
 

 
 
 
 
 
 
 

 

default
serial_rcvr_def_tb

    TIMEOUT1000000


 
 
 

fifo_default
serial_rcvr_fifo_tb

    TIMEOUT1000000


 
 

 
 

 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`logic`
12			`serial_rcvr`
13
14			`2`
15			`_`
16			`_`
17			`_`
18			`VARIANT`
19
20	135	jt_eaton
21
22			`TestBenches`
23			`sim`
24			`testbenches`
25			`testbench`
26			`version`
27
28
29			`Fpgas`
30			`syn`
31			`ise`
32			`chip`
33			`variant`
34
35
36	131	jt_eaton
37	135	jt_eaton
38
39	131	jt_eaton
40
41			`/doc`
42
43
44
45	134	jt_eaton
46	131	jt_eaton
47	134	jt_eaton
48			`default`
49			`def`
50
51			`WIDTH8`
52			`SIZE4`
53			`SAMPLE4'b0111`
54			`START_VALUE1'b0`
55			`STOP_VALUE1'b1`
56
57
58	131	jt_eaton
59
60
61	134	jt_eaton
62			`fifo`
63			`fifo`
64
65			`WIDTH8`
66			`SIZE4`
67			`SAMPLE4'b0111`
68			`START_VALUE1'b0`
69			`STOP_VALUE1'b1`
70			`RX_FIFO_SIZE4`
71			`RX_FIFO_WORDS16`
72
73
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101	131	jt_eaton
102
103
104			`serial_rcvr/sim`
105
106
107
108
109
110
111
112
113
114			`serial_rcvr_def_tb`
115			`def_tb`
116	134	jt_eaton	`default`
117	131	jt_eaton
118			`PERIOD40`
119			`TIMEOUT100000`
120
121
122
123			`serial_rcvr_defTB.test.dut`
124
125
126
127			`icaruscoverage`
128
129
130
131
132
133
134
135
136			`serial_rcvr_fifo_tb`
137			`fifo_tb`
138	134	jt_eaton	`fifo`
139	131	jt_eaton
140			`PERIOD40`
141			`TIMEOUT1000`
142
143
144
145			`serial_rcvr_fifo`
146			`TB.test.dut`
147
148
149
150			`icaruscoverage`
151
152
153
154
155
156
157
158
159
160			`serial_rcvr_def_lint`
161			`def_lint`
162	134	jt_eaton	`default`
163	131	jt_eaton
164			`rtl_check`
165
166
167
168
169
170
171			`serial_rcvr_fifo_lint`
172			`fifo_lint`
173	134	jt_eaton	`fifo`
174	131	jt_eaton
175			`rtl_check`
176
177
178
179
180
181
182
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185
186
187
188			`default`
189	134	jt_eaton	`default`
190	131	jt_eaton	`serial_rcvr_def_lint`
191
192
193
194
195
196			`fifo_default`
197	134	jt_eaton	`fifo`
198	131	jt_eaton	`serial_rcvr_fifo_lint`
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213			`default`
214			`serial_rcvr_def_tb`
215
216			`TIMEOUT1000000`
217
218
219
220
221
222
223			`fifo_default`
224			`serial_rcvr_fifo_tb`
225
226			`TIMEOUT1000000`
227
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