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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
serial_rcvr
fifo
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
 
    
      
        reset
        reset
      
    
 
        
      
 
 
  
 
 
 

 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      serial_rcvr_fifo
    
  

 
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
      
        
        ../verilog/fifo
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr_fifo
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/serial_rcvr_fifo
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
  
 
 
 
 
  
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
       
 
              
              Hierarchical
      Hierarchical
                        
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
 
 
 
pad_in
wire
in

 
rcv_stb
wire
in

 
data_out
wire
out
WIDTH-10

 
parity_error
wire
out

 
stop_error
wire
out

 
data_avail
wire
out

 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`fifo`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68	131	jt_eaton
69	135	jt_eaton
70
71			`reset`
72			`reset`
73
74
75
76
77
78	131	jt_eaton
79
80	135	jt_eaton
81	131	jt_eaton
82	135	jt_eaton
83	131	jt_eaton
84	135	jt_eaton
85	131	jt_eaton
86
87
88	135	jt_eaton
89	131	jt_eaton
90	133	jt_eaton
91	131	jt_eaton
92
93
94
95	135	jt_eaton
96			`gen_verilog`
97			`104.0`
98			`none`
99			`:common:`
100			`tools/verilog/gen_verilog`
101
102
103			`destination`
104			`serial_rcvr_fifo`
105
106
107
108	131	jt_eaton
109
110
111
112
113
114	135	jt_eaton
115	131	jt_eaton
116
117
118
119	135	jt_eaton
120	131	jt_eaton
121	135	jt_eaton
122			`fs-common`
123	131	jt_eaton
124
125	135	jt_eaton
126
127			`../verilog/top.body`
128			`verilogSourcefragment`
129
130	131	jt_eaton
131
132	135	jt_eaton
133
134			`../verilog/fifo`
135			`verilogSourcefragment`
136
137	131	jt_eaton
138
139
140	135	jt_eaton
141	131	jt_eaton
142
143
144	135	jt_eaton
145			`fs-sim`
146	131	jt_eaton
147	135	jt_eaton
148
149			`../verilog/copyright`
150			`verilogSourceinclude`
151
152	134	jt_eaton
153	135	jt_eaton
154
155			`../verilog/common/serial_rcvr_fifo`
156			`verilogSourcemodule`
157
158	131	jt_eaton
159	135	jt_eaton
160			`dest_dir`
161			`../views/sim/`
162			`verilogSourcelibraryDir`
163
164	131	jt_eaton
165
166
167	135	jt_eaton
168	131	jt_eaton
169
170	135	jt_eaton
171			`fs-syn`
172	131	jt_eaton
173	134	jt_eaton
174	135	jt_eaton
175
176			`../verilog/copyright`
177			`verilogSourceinclude`
178
179	131	jt_eaton
180	135	jt_eaton
181
182			`../verilog/common/serial_rcvr_fifo`
183			`verilogSourcemodule`
184
185	131	jt_eaton
186	135	jt_eaton
187			`dest_dir`
188			`../views/syn/`
189			`verilogSourcelibraryDir`
190
191	131	jt_eaton
192
193	135	jt_eaton
194	131	jt_eaton
195
196
197
198	135	jt_eaton
199	131	jt_eaton
200
201
202
203	135	jt_eaton
204	131	jt_eaton
205
206	135	jt_eaton
207
208			`Hierarchical`
209
210
211
212	131	jt_eaton
213
214
215
216	135	jt_eaton
217
218	131	jt_eaton
219	135	jt_eaton
220			`Hierarchical`
221			`Hierarchical`
222
223	131	jt_eaton
224
225	135	jt_eaton
226			`verilog`
227
228
229			`ipxact:library="Testbench"`
230			`ipxact:name="toolflow"`
231			`ipxact:version="verilog"/>`
232
233
234	131	jt_eaton
235
236
237
238
239	135	jt_eaton
240			`common:common:`
241			`Verilog`
242
243
244			`fs-common`
245
246
247	131	jt_eaton
248
249
250	135	jt_eaton
251			`sim:Simulation:`
252			`Verilog`
253
254
255			`fs-sim`
256
257
258	131	jt_eaton
259
260	135	jt_eaton
261			`syn:Synthesis:`
262			`Verilog`
263
264
265			`fs-syn`
266
267
268	131	jt_eaton
269
270	135	jt_eaton
271			`doc`
272
273
274			`ipxact:library="Testbench"`
275			`ipxact:name="toolflow"`
276			`ipxact:version="documentation"/>`
277
278			`:Documentation:`
279			`Verilog`
280
281	131	jt_eaton
282
283
284	135	jt_eaton
285	131	jt_eaton
286
287
288
289
290	135	jt_eaton
291	131	jt_eaton
292
293	135	jt_eaton	`edge_enable`
294			`wire`
295			`in`
296
297	131	jt_eaton
298	135	jt_eaton	`parity_enable`
299			`wire`
300			`in`
301
302	131	jt_eaton
303	135	jt_eaton	`parity_type`
304			`wire`
305			`in`
306
307	131	jt_eaton
308	135	jt_eaton	`parity_force`
309			`wire`
310			`in`
311
312	131	jt_eaton
313
314
315
316	135	jt_eaton	`pad_in`
317			`wire`
318			`in`
319
320	131	jt_eaton
321	135	jt_eaton	`rcv_stb`
322			`wire`
323			`in`
324
325	131	jt_eaton
326	135	jt_eaton	`data_out`
327			`wire`
328			`out`
329			`WIDTH-10`
330
331	131	jt_eaton
332	135	jt_eaton	`parity_error`
333			`wire`
334			`out`
335
336	131	jt_eaton
337	135	jt_eaton	`stop_error`
338			`wire`
339			`out`
340
341	131	jt_eaton
342	135	jt_eaton	`data_avail`
343			`wire`
344			`out`
345
346	131	jt_eaton
347	135	jt_eaton
348	131	jt_eaton
349	135	jt_eaton
350
351
352
353
354
355
356
357
358
359
360