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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_dut.params.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
logic
serial_rcvr
def_dut.params

                
                        
                                Dut
                                
                        
                
 
 
      
 
              
              Dut
              
    Dut
 
 
              
      

    WIDTH8
    SIZE4
    SAMPLE4'b0111
    START_VALUE1'b0
    STOP_VALUE1'b1




Line No.	Rev	Author	Line
1	131	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`logic`
17			`serial_rcvr`
18			`def_dut.params`
19
20
21
22			`Dut`
23
24
25
26	131	jt_eaton
27	135	jt_eaton
28
29	131	jt_eaton
30	135	jt_eaton
31			`Dut`
32
33			`Dut`
34
35
36
37
38
39			`WIDTH8`
40			`SIZE4`
41			`SAMPLE4'b0111`
42			`START_VALUE1'b0`
43			`STOP_VALUE1'b1`
44
45
46

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_dut.params.xml] - Blame information for rev 135