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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_fifo_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
serial_rcvr
fifo_lint
 
 
 

 
 
       
 
 
 
              
              Dut
              
              
                                   ipxact:library="logic"
                                   ipxact:name="serial_rcvr"
                                   ipxact:version="fifo_dut.params"/>
              
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 
 
 
 

 
 
 
 
 
  
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/serial_rcvr_fifo_lint
        verilogSourcemodule
      
 
    
 
 
 
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`fifo_lint`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`Dut`
53
54
55			`ipxact:library="logic"`
56			`ipxact:name="serial_rcvr"`
57			`ipxact:version="fifo_dut.params"/>`
58
59
60	131	jt_eaton
61
62
63	135	jt_eaton
64			`lint`
65			`:Lint:`
66			`Verilog`
67			`fs-lint`
68
69	131	jt_eaton
70
71	135	jt_eaton
72			`rtl_check`
73
74
75			`ipxact:library="Testbench"`
76			`ipxact:name="toolflow"`
77			`ipxact:version="rtl_check"/>`
78
79
80	131	jt_eaton
81	135	jt_eaton
82	131	jt_eaton
83
84
85
86
87	135	jt_eaton
88	131	jt_eaton
89
90
91
92
93	135	jt_eaton
94	131	jt_eaton
95
96
97
98	135	jt_eaton
99			`fs-lint`
100	131	jt_eaton
101	135	jt_eaton
102
103			`../verilog/lint/serial_rcvr_fifo_lint`
104			`verilogSourcemodule`
105
106	131	jt_eaton
107	135	jt_eaton
108	131	jt_eaton
109
110
111	135	jt_eaton
112	131	jt_eaton
113
114
115
116
117	135	jt_eaton

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_fifo_lint.xml] - Blame information for rev 135