Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

logic

spi_interface

def

 slave_clk

        clk

        clk

 slave_reset

        reset

        reset

 spi

        clk

        spi_clk_pad_in

        mosi

        spi_mosi_pad_in

        miso

        spi_miso_pad_out

        sel_n

        spi_sel_n_pad_in

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      spi_interface_def

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      spi_interface_def

                                Hierarchical

              Hierarchical

                       Hierarchical

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

busy

wire

out

tx_data

wire

in

150

rx_data

wire

out

150

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/sim/spi_interface_def

        verilogSourcemodule

        ../verilog/spi_slave.v

        verilogSourcemodule

        ../verilog/top.body

        verilogSourcefragment

        ../verilog/top.sim

        verilogSourcefragment

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/syn/spi_interface_def

        verilogSourcemodule

        ../verilog/spi_slave.v

        verilogSourcemodule

        ../verilog/top.body

        verilogSourcefragment

        ../verilog/top.syn

        verilogSourcefragment

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir