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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [spi_interface/] [sim/] [testbenches/] [xml/] [spi_interface_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
spi_interface
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      spi_interface_def_tb
    
  

 
 
 
 

 
 
 
 

 
 

  SPI_CLKCNT4'h4
  SPI_SIZE4

 
 
       
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="spi_interface"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="spi_interface"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/spi_interface_def_tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/spi_interface_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 


Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`spi_interface`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`spi_interface_def_tb`
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77			`SPI_CLKCNT4'h4`
78			`SPI_SIZE4`
79
80
81
82
83
84
85			`Params`
86
87
88			`ipxact:library="logic"`
89			`ipxact:name="spi_interface"`
90			`ipxact:version="def_dut.params"/>`
91
92
93
94
95
96
97
98			`Bfm`
99
100			`ipxact:library="logic"`
101			`ipxact:name="spi_interface"`
102			`ipxact:version="bfm.design"/>`
103
104
105
106
107
108			`icarus`
109
110
111			`ipxact:library="Testbench"`
112			`ipxact:name="toolflow"`
113			`ipxact:version="icarus"/>`
114
115
116
117
118
119
120
121
122
123			`common:common:`
124			`Verilog`
125
126
127			`fs-common`
128
129
130
131
132
133			`sim:Simulation:`
134			`Verilog`
135
136
137			`fs-sim`
138
139
140
141
142
143			`lint:Lint:`
144			`Verilog`
145
146
147			`fs-lint`
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171			`fs-common`
172
173
174
175
176			`../verilog/top.body`
177			`verilogSourcefragment`
178
179
180
181
182
183
184
185
186
187			`fs-sim`
188
189
190
191			`../verilog/common/spi_interface_def_tb`
192			`verilogSourcemodule`
193
194
195
196
197
198
199
200
201
202
203
204
205
206			`fs-lint`
207
208
209
210			`../verilog/common/spi_interface_def_tb`
211			`verilogSourcemodule`
212
213
214
215
216
217
218
219
220
221
222
223
224
225

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [spi_interface/] [sim/] [testbenches/] [xml/] [spi_interface_def_tb.xml] - Blame information for rev 135