URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [componentCfg.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
logic
uart
 
 
2
_
_
_
VARIANT
 

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 
 
 
 
 

 
 
   default
   def
                  
                  PRESCALE5'b01100
                  PRE_SIZE5
                  SIZE8
                  DIV0
                  DIV_SIZE4
                  
          
 
 
 
 
   rxtx
   rxtx
                  
                  PRESCALE5'b01100
                  PRE_SIZE5
                  SIZE8
                  DIV0
                  DIV_SIZE4
                  TX_FIFO_SIZE3
                  TX_FIFO_WORDS8
                  RX_FIFO_SIZE3
                  RX_FIFO_WORDS8
                  
          
 
 
 
   rx
   rx
                 
                 PRESCALE5'b01100
                 PRE_SIZE5
                 SIZE8
                 DIV0
                 DIV_SIZE4
                 RX_FIFO_SIZE3
                 RX_FIFO_WORDS8
                 
          
 
 
   tx
   tx
                
                PRESCALE5'b01100
                PRE_SIZE5
                SIZE8
                DIV0
                DIV_SIZE4
                TX_FIFO_SIZE3
                TX_FIFO_WORDS8
                
          
 
 
 
 
 
 
 
 

 
 
uart/sim
 
 
 
 
 
 

 
 

uart_def_tb
default
def_tb

    PERIOD40
    TIMEOUT100000


  
  uart_defTB.test.dut
  


  icaruscoverage


 
 

uart_rx_tb
rx_tb
rx

    PERIOD40
    TIMEOUT100000


  
  uart_rxTB.test.dut
  


  icaruscoverage


 
 
 

uart_tx_tb
tx_tb
tx

    PERIOD40
    TIMEOUT100000


  
  uart_txTB.test.dut
  


  icaruscoverage


 
 
 
 
 

uart_rxtx_tb
rxtx_tb
rxtx

    PERIOD40
    TIMEOUT100000


  icarus


 
 
 
 
 
 

uart_def_lint
def_lint
default

  rtl_check


 
 

uart_rx_lint
rx_lint
rx

  rtl_check


 
 
 

uart_tx_lint
tx_lint
tx

  rtl_check


 
 

uart_rxtx_lint
rxtx_lint
rxtx

  rtl_check


 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 

 

default
uart_def_lint

 

divide
uart_def_lint

DIV1


 

rx_default
uart_rx_lint

RX_FIFO_SIZE4
RX_FIFO_WORDS16


 

tx_default
uart_tx_lint

TX_FIFO_SIZE4
TX_FIFO_WORDS16


 

rxtx_default
uart_rxtx_lint

TX_FIFO_SIZE3
TX_FIFO_WORDS8
RX_FIFO_SIZE4
RX_FIFO_WORDS16


 

 
 
 
 
 
 

 

default
uart_def_tb

TIMEOUT3000000


 

divide
uart_def_tb

DIV1
TIMEOUT3000000


 

rx_default
uart_rx_tb

RX_FIFO_SIZE4
RX_FIFO_WORDS16
TIMEOUT3000000


 

tx_default
uart_tx_tb

TX_FIFO_SIZE4
TX_FIFO_WORDS16
TIMEOUT3000000


 

rxtx_default
uart_rxtx_tb

TX_FIFO_SIZE3
TX_FIFO_WORDS8
RX_FIFO_SIZE4
RX_FIFO_WORDS16
TIMEOUT3000000


 

 

 
 
 
 

 
 
 
 
 
 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`logic`
12			`uart`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21	135	jt_eaton
22
23			`TestBenches`
24			`sim`
25			`testbenches`
26			`testbench`
27			`version`
28
29
30			`Fpgas`
31			`syn`
32			`ise`
33			`chip`
34			`variant`
35
36
37	131	jt_eaton
38	135	jt_eaton
39
40	131	jt_eaton
41
42			`/doc`
43
44
45
46
47
48
49
50	134	jt_eaton
51
52
53			`default`
54			`def`
55
56			`PRESCALE5'b01100`
57			`PRE_SIZE5`
58			`SIZE8`
59			`DIV0`
60			`DIV_SIZE4`
61
62
63
64
65
66
67			`rxtx`
68			`rxtx`
69
70			`PRESCALE5'b01100`
71			`PRE_SIZE5`
72			`SIZE8`
73			`DIV0`
74			`DIV_SIZE4`
75			`TX_FIFO_SIZE3`
76			`TX_FIFO_WORDS8`
77			`RX_FIFO_SIZE3`
78			`RX_FIFO_WORDS8`
79
80
81
82
83
84			`rx`
85			`rx`
86
87			`PRESCALE5'b01100`
88			`PRE_SIZE5`
89			`SIZE8`
90			`DIV0`
91			`DIV_SIZE4`
92			`RX_FIFO_SIZE3`
93			`RX_FIFO_WORDS8`
94
95
96
97
98			`tx`
99			`tx`
100
101			`PRESCALE5'b01100`
102			`PRE_SIZE5`
103			`SIZE8`
104			`DIV0`
105			`DIV_SIZE4`
106			`TX_FIFO_SIZE3`
107			`TX_FIFO_WORDS8`
108
109
110
111
112
113
114
115
116
117
118	131	jt_eaton
119
120
121			`uart/sim`
122
123
124
125
126
127
128
129
130
131
132			`uart_def_tb`
133	134	jt_eaton	`default`
134	131	jt_eaton	`def_tb`
135
136			`PERIOD40`
137			`TIMEOUT100000`
138
139
140
141			`uart_defTB.test.dut`
142
143
144
145			`icaruscoverage`
146
147
148
149
150
151			`uart_rx_tb`
152			`rx_tb`
153	134	jt_eaton	`rx`
154	131	jt_eaton
155			`PERIOD40`
156			`TIMEOUT100000`
157
158
159
160			`uart_rxTB.test.dut`
161
162
163
164			`icaruscoverage`
165
166
167
168
169
170
171			`uart_tx_tb`
172			`tx_tb`
173	134	jt_eaton	`tx`
174	131	jt_eaton
175			`PERIOD40`
176			`TIMEOUT100000`
177
178
179
180			`uart_txTB.test.dut`
181
182
183
184			`icaruscoverage`
185
186
187
188
189
190
191
192
193			`uart_rxtx_tb`
194			`rxtx_tb`
195	134	jt_eaton	`rxtx`
196	131	jt_eaton
197			`PERIOD40`
198			`TIMEOUT100000`
199
200
201			`icarus`
202
203
204
205
206
207
208
209
210
211			`uart_def_lint`
212	134	jt_eaton	`def_lint`
213			`default`
214	131	jt_eaton
215			`rtl_check`
216
217
218
219
220
221			`uart_rx_lint`
222			`rx_lint`
223	134	jt_eaton	`rx`
224	131	jt_eaton
225			`rtl_check`
226
227
228
229
230
231
232			`uart_tx_lint`
233			`tx_lint`
234	134	jt_eaton	`tx`
235	131	jt_eaton
236			`rtl_check`
237
238
239
240
241
242			`uart_rxtx_lint`
243			`rxtx_lint`
244	134	jt_eaton	`rxtx`
245	131	jt_eaton
246			`rtl_check`
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269			`default`
270			`uart_def_lint`
271
272
273
274			`divide`
275			`uart_def_lint`
276
277			`DIV1`
278
279
280
281
282			`rx_default`
283			`uart_rx_lint`
284
285			`RX_FIFO_SIZE4`
286			`RX_FIFO_WORDS16`
287
288
289
290
291			`tx_default`
292			`uart_tx_lint`
293
294			`TX_FIFO_SIZE4`
295			`TX_FIFO_WORDS16`
296
297
298
299
300			`rxtx_default`
301			`uart_rxtx_lint`
302
303			`TX_FIFO_SIZE3`
304			`TX_FIFO_WORDS8`
305			`RX_FIFO_SIZE4`
306			`RX_FIFO_WORDS16`
307
308
309
310
311
312
313
314
315
316
317
318
319
320			`default`
321			`uart_def_tb`
322
323			`TIMEOUT3000000`
324
325
326
327
328			`divide`
329			`uart_def_tb`
330
331			`DIV1`
332			`TIMEOUT3000000`
333
334
335
336
337			`rx_default`
338			`uart_rx_tb`
339
340			`RX_FIFO_SIZE4`
341			`RX_FIFO_WORDS16`
342			`TIMEOUT3000000`
343
344
345
346
347			`tx_default`
348			`uart_tx_tb`
349
350			`TX_FIFO_SIZE4`
351			`TX_FIFO_WORDS16`
352			`TIMEOUT3000000`
353
354
355
356
357			`rxtx_default`
358			`uart_rxtx_tb`
359
360			`TX_FIFO_SIZE3`
361			`TX_FIFO_WORDS8`
362			`RX_FIFO_SIZE4`
363			`RX_FIFO_WORDS16`
364			`TIMEOUT3000000`
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382