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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_bfm.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
bfm.design
 
 
 

 
 
   
      clk
      
      
    
 
   
      reset
      
      
    
 
 
   
      txd_pad_out
      
    
 
   
      rxd_pad_in
      
    
 
   
      parity_enable
      
    
 
   
      txd_parity
      
    
 
   
      txd_force_parity
      
    
 
   
      txd_data_in
      
    
 
   
      txd_buffer_empty
      
    
 
   
      txd_load
      
    
 
   
      txd_break
      
    
 
   
      rxd_parity
      
    
 
   
      rxd_force_parity
      
    
 
 
   
      rxd_data_out
      
    
 
 
   
      rxd_data_avail
      
    
 
 
   
      rxd_data_avail_stb
      
    
 
   
      rxd_stop_error
      
    
 
 
   
      rxd_parity_error
      
    
 
 

 
 
 
 
 
 
 
 

 
 
 

uart_host 

 
 
 

uart_model 

 UART_MODEL_CLKCNT
 UART_MODEL_SIZE


 
 
 
 

 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`bfm.design`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton
48			`clk`
49
50
51
52	131	jt_eaton
53	135	jt_eaton
54			`reset`
55
56
57
58	131	jt_eaton
59
60	135	jt_eaton
61			`txd_pad_out`
62
63
64	131	jt_eaton
65	135	jt_eaton
66			`rxd_pad_in`
67
68
69	131	jt_eaton
70	135	jt_eaton
71			`parity_enable`
72
73
74	131	jt_eaton
75	135	jt_eaton
76			`txd_parity`
77
78
79	131	jt_eaton
80	135	jt_eaton
81			`txd_force_parity`
82
83
84	131	jt_eaton
85	135	jt_eaton
86			`txd_data_in`
87
88
89	131	jt_eaton
90	135	jt_eaton
91			`txd_buffer_empty`
92
93
94	131	jt_eaton
95	135	jt_eaton
96			`txd_load`
97
98
99	131	jt_eaton
100	135	jt_eaton
101			`txd_break`
102
103
104	131	jt_eaton
105	135	jt_eaton
106			`rxd_parity`
107
108
109	131	jt_eaton
110	135	jt_eaton
111			`rxd_force_parity`
112
113
114	131	jt_eaton
115
116	135	jt_eaton
117			`rxd_data_out`
118
119
120	131	jt_eaton
121
122	135	jt_eaton
123			`rxd_data_avail`
124
125
126	131	jt_eaton
127
128	135	jt_eaton
129			`rxd_data_avail_stb`
130
131
132	131	jt_eaton
133	135	jt_eaton
134			`rxd_stop_error`
135
136
137	131	jt_eaton
138
139	135	jt_eaton
140			`rxd_parity_error`
141
142
143	131	jt_eaton
144
145	135	jt_eaton
146	131	jt_eaton
147
148
149
150
151
152
153
154	135	jt_eaton
155	131	jt_eaton
156
157
158	135	jt_eaton
159			`uart_host`
160
161	131	jt_eaton
162
163
164	135	jt_eaton
165			`uart_model`
166
167			`UART_MODEL_CLKCNT`
168			`UART_MODEL_SIZE`
169
170
171	131	jt_eaton
172
173
174
175	135	jt_eaton
176	131	jt_eaton
177
178
179
180
181
182
183
184	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_bfm.design.xml] - Blame information for rev 135