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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
def_tb
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_def_tb
    
  

 
 
 

 
 
 
 

 

    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
 
       
 
 
 
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/common/uart_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/uart_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`def_tb`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`uart_def_tb`
58
59
60
61	131	jt_eaton
62
63
64	135	jt_eaton
65	131	jt_eaton
66
67
68
69	135	jt_eaton
70	131	jt_eaton
71	135	jt_eaton
72			`UART_MODEL_CLKCNT4'hc`
73			`UART_MODEL_SIZE4`
74			`DIVIDER4'b0000`
75
76	131	jt_eaton
77
78
79	135	jt_eaton
80	131	jt_eaton
81
82
83
84	135	jt_eaton
85			`Params`
86
87
88			`ipxact:library="logic"`
89			`ipxact:name="uart"`
90			`ipxact:version="def_dut.params"/>`
91
92
93	131	jt_eaton
94
95
96	135	jt_eaton
97			`Bfm`
98
99			`ipxact:library="logic"`
100			`ipxact:name="uart"`
101			`ipxact:version="bfm.design"/>`
102
103	131	jt_eaton
104
105	135	jt_eaton
106			`icarus`
107
108
109			`ipxact:library="Testbench"`
110			`ipxact:name="toolflow"`
111			`ipxact:version="icarus"/>`
112
113
114	131	jt_eaton
115
116
117
118
119	135	jt_eaton
120			`common:common:`
121			`Verilog`
122
123
124			`fs-common`
125
126
127	131	jt_eaton
128
129
130	135	jt_eaton
131			`sim:Simulation:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138	131	jt_eaton
139
140
141
142	135	jt_eaton
143			`lint:Lint:`
144			`Verilog`
145
146
147			`fs-lint`
148
149
150	131	jt_eaton
151
152	135	jt_eaton
153	131	jt_eaton
154
155
156
157
158
159
160
161	135	jt_eaton
162	131	jt_eaton
163
164
165	135	jt_eaton
166	131	jt_eaton
167	135	jt_eaton
168			`fs-common`
169	131	jt_eaton
170	135	jt_eaton
171
172			`../verilog/tb.ext`
173			`verilogSourcefragment`
174
175	131	jt_eaton
176	135	jt_eaton
177	131	jt_eaton
178	135	jt_eaton
179			`fs-sim`
180	131	jt_eaton
181	135	jt_eaton
182
183			`../verilog/common/uart_def_tb`
184			`verilogSourcemodule`
185
186	131	jt_eaton
187
188
189	135	jt_eaton
190	131	jt_eaton
191
192	135	jt_eaton
193			`fs-lint`
194	131	jt_eaton
195	135	jt_eaton
196
197			`../verilog/common/uart_def_tb`
198			`verilogSourcemodule`
199
200	131	jt_eaton
201
202
203	135	jt_eaton
204	131	jt_eaton
205
206
207	135	jt_eaton
208	131	jt_eaton
209
210
211
212
213	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_def_tb.xml] - Blame information for rev 135