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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_duth.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
logic
uart
rx_duth.design

 

clk



 

cts_out



 

cts_pad_in



 

divider_in



 

parity_enable



 

reset



 

rts_in



 

rts_pad_out



 

rxd_data_avail



 
 
 

rxd_data_avail_stb



 

rxd_data_out



 

rxd_force_parity



 

rxd_pad_in



 

rxd_parity



 

rxd_parity_error



 

rxd_stop_error



 

txd_break



 

txd_buffer_empty



 

txd_data_in



 

txd_force_parity



 

txd_load



 

txd_pad_out



 

txd_parity



 
 


 

dut


 DIV
 DIV_SIZE
 PRESCALE
 PRE_SIZE
 RX_FIFO_SIZE
 RX_FIFO_WORDS
 SIZE





Line No.	Rev	Author	Line
1	133	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`logic`
17			`uart`
18			`rx_duth.design`
19
20	133	jt_eaton
21	135	jt_eaton
22			`clk`
23
24
25
26	133	jt_eaton
27	135	jt_eaton
28			`cts_out`
29
30
31
32	133	jt_eaton
33	135	jt_eaton
34			`cts_pad_in`
35
36
37
38	133	jt_eaton
39	135	jt_eaton
40			`divider_in`
41
42
43
44	133	jt_eaton
45	135	jt_eaton
46			`parity_enable`
47
48
49
50	133	jt_eaton
51	135	jt_eaton
52			`reset`
53
54
55
56	133	jt_eaton
57	135	jt_eaton
58			`rts_in`
59
60
61
62	133	jt_eaton
63	135	jt_eaton
64			`rts_pad_out`
65
66
67
68	133	jt_eaton
69	135	jt_eaton
70			`rxd_data_avail`
71
72
73
74	133	jt_eaton
75
76
77	135	jt_eaton
78			`rxd_data_avail_stb`
79
80
81
82	133	jt_eaton
83	135	jt_eaton
84			`rxd_data_out`
85
86
87
88	133	jt_eaton
89	135	jt_eaton
90			`rxd_force_parity`
91
92
93
94	133	jt_eaton
95	135	jt_eaton
96			`rxd_pad_in`
97
98
99
100	133	jt_eaton
101	135	jt_eaton
102			`rxd_parity`
103
104
105
106	133	jt_eaton
107	135	jt_eaton
108			`rxd_parity_error`
109
110
111
112	133	jt_eaton
113	135	jt_eaton
114			`rxd_stop_error`
115
116
117
118	133	jt_eaton
119	135	jt_eaton
120			`txd_break`
121
122
123
124	133	jt_eaton
125	135	jt_eaton
126			`txd_buffer_empty`
127
128
129
130	133	jt_eaton
131	135	jt_eaton
132			`txd_data_in`
133
134
135
136	133	jt_eaton
137	135	jt_eaton
138			`txd_force_parity`
139
140
141
142	133	jt_eaton
143	135	jt_eaton
144			`txd_load`
145
146
147
148	133	jt_eaton
149	135	jt_eaton
150			`txd_pad_out`
151
152
153
154	133	jt_eaton
155	135	jt_eaton
156			`txd_parity`
157
158
159
160	133	jt_eaton
161
162	135	jt_eaton
163
164
165
166			`dut`
167
168
169			`DIV`
170			`DIV_SIZE`
171			`PRESCALE`
172			`PRE_SIZE`
173			`RX_FIFO_SIZE`
174			`RX_FIFO_WORDS`
175			`SIZE`
176
177
178
179

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_duth.design.xml] - Blame information for rev 135